mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet - Page 93

• Manufacturer Part Number: mpc8536e
• Description: Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The following sections describe the SerDes reference clock requirements and some application information.
2.20.2.1
Figure 58
Freescale Semiconductor
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The supply voltage requirements for X2V
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the Differential Mode and
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to SnGND (xcorevss)
The input amplitude requirement
— This requirement is described in detail in the following sections.
shows a receiver reference diagram of the SerDes reference clocks.
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND (xcorevss)
followed by on-chip AC-coupling.
Single-ended Mode description below for further detailed requirements.
maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), since the input is AC-coupled on-chip.
while the minimum common mode input level is 0.1V above SnGND (xcorevss). For example, a clock with a
50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA
(0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800mV with the
common mode voltage at 400mV.
DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
SerDes Reference Clock Receiver Characteristics
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Figure 58. Receiver of SerDes Reference Clocks
SDn_REF_CLK
SDn_REF_CLK
DD
are specified in
50 Ω
50 Ω
Table 2
Input
Amp
and
Table
3.
High-Speed Serial Interfaces
Figure
58.
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