mpc8641 Freescale Semiconductor, Inc, mpc8641 Datasheet - Page 114

• Manufacturer Part Number: mpc8641
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Thermal
example, assuming a T
(P
Die-junction temperature: T
For this example, a R
below the maximum value of
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common
figure-of-merit used for comparing the thermal performance of various microelectronic packaging
technologies, one should exercise caution when only using this metric in determining thermal management
because no single parameter can adequately describe three-dimensional heat flow. The final die-junction
operating temperature is not only a function of the component-level thermal resistance, but the
system-level design and its operating conditions. In addition to the component's power consumption, a
number of factors affect the final operating die-junction temperature—airflow, board population (local
heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect
technology, system air temperature rise, altitude, and so on.
Due to the complexity and variety of system-level boundary conditions for today's microelectronic
equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction)
may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as
well as system-level designs.
For system thermal modeling, the MPC8641 thermal model is shown in
to represent this device. The die is modeled as 12.4x15.3 mm at a thickness of 0.86 mm. See
“Power
33x33x1.2 mm with orthotropic conductivity: 13.5 W/(m
z-direction. The die is centered on the substrate. The bump/underfill layer is modeled as a collapsed
thermal resistance between the die and substrate with a conductivity of 5.3 W/(m
dimension of 0.07 mm. Because the bump/underfill is modeled with zero physical dimension (collapsed
height), the die thickness was slightly enlarged to provide the correct height. The C5 solder layer is
modeled as a cuboid with dimensions 33x33x0.4 mm and orthotropic thermal conductivity of 0.034 W/(m
• K) in the xy-plane and 9.6 W/(m • K) in the z-direction. An LGA solder layer would be modeled as a
collapsed thermal resistance with thermal conductivity of 9.6W/(m • K) and an effective height of 0.1 mm.
The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual
dimensions.
114
d
) of 43.4 W, the following expression for T
Characteristics” for power dissipation details. The substrate is modeled as a single block
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
θsa
i
of 30 C, a T
value of 1.32 C/W or less is required to maintain the die junction temperature
j
Table
= 30 C + 5 C + (0.1 C/W + 0.2 C/W + θ
2.
r
of 5 C, a package R
j
is obtained:
•
K) in the xy-plane and 5.3 W/(m
θJC
= 0.1, and a typical power consumption
Figure
sa
) × 43.4 W
62. Four cuboids are used
•
K) in the thickness
Freescale Semiconductor
•
Section 3,
K) in the