mpc5125 Freescale Semiconductor, Inc, mpc5125 Datasheet - Page 83

• Manufacturer Part Number: mpc5125
• Description: Mpc5125 Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

5.4
The MPC5125 requires external pullup or pulldown resistors on certain pins.
5.4.1
The MPC5125 requires a pulldown resistor on the test pin TEST.
5.5
The MPC5125 has an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a common on-chip
processor (COP) interface, which shares the IEEE 1149.1 JTAG port.
The COP interface provides access to the MPC5125’s embedded e300 processor and to other on-chip resources. This interface
provides a means for executing test routines and for performing software development and debug functions.
5.5.1
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
5.5.1.1
The JTAG interface can control the direction of the MPC5125 I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5125 comes out of power-on reset; do this by asserting TRST before PORESET is released.
For more details, see the Reset and JTAG Timing Specification.
5.5.2
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
5.5.2.1
The MPC5125 functional pin interface and internal logic provides access to the embedded e300 processor core through the
Freescale standard COP / BDM interface.
COP / BDM connector order.
Freescale Semiconductor
Required assertion of TRST
PORESET
Pullup/Pulldown Resistor Requirements
JTAG
Pulldown Resistor Requirements for TEST Pin
JTAG_TRST
e300 COP / BDM Interface
TRST and PORESET
Boards Interfacing the JTAG Port via a COP Connector
TRST
MPC5125 Microcontroller Data Sheet, Rev. 3
Table 49
Figure 50. PORESET vs. TRST
gives the COP / BDM interface signals. The pin order shown reflects only the
Optional assertion of TRST
System Design Information
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