spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 14

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spc560p50l3

Manufacturer Part Number
spc560p50l3
Description
32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
Manufacturer
STMicroelectronics
Datasheet

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Overview of the SPC560Px
3.2.7
3.2.8
14/31
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the resource can not preempt each other.
The INTC provides the following features:
System clocks and clock generation
The following list summarizes the system clock and clock generation on the SPC560Px:
Frequency Modulated PLL (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz
input clock. Further, the FMPLL supports programmable frequency modulation of the
system clock. The PLL multiplication factor, output clock divider ratio are all software
configurable.
a. To be confirmed
Unique 9-bit vector for each separate interrupt source
8 software triggerable interrupt sources
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
Ability to modify the ISR or task priority.
2 external high priority interrupts directly accessing the main core and IOP critical
interrupt mechanism
Lock detect circuitry continuously monitors lock status
Loss Of Clock (LOC) detection for PLL outputs
Programmable output clock divider (÷1, ÷2, ÷4, ÷8)
FlexPWM module and eTimer module can run on an independent clock source
On-chip oscillator with automatic level control
Internal 16 MHz RC oscillator for rapid start-up and safe mode
Modifying the priority can be used to implement the priority ceiling protocol for
accessing shared resources.
Supports frequency trimming by user application
Doc ID 13950 Rev 5
(a)
SPC560P44Lx, SPC560P50Lx

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