tspc106 ATMEL Corporation, tspc106 Datasheet - Page 14

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Multiple Processor
Signals
Table 5. Multiple Processor Signals
14
Signal
BG1
DIRTY_OUT
BG2
TWE
BG3
DCS
BR1
DIRTY_IN
BR2
TV
BR3
BA0
DBG1
TOE
DBG2
DWE0
DBG3
DWE1
TSPC106A
Signal Name
Bus grant 1
Bus grant 2
Bus grant 3
Bus request 1
Bus request 2
Bus request 3
Data bus grant 1
Data bus grant 2
Data bus grant 3
When a system implementation uses more than one 60x processor, nine of the internal
L2 cache controller signals change their functions.
Note that in a multi-processor system, with the exception of the bus grant, bus request
and data bus grant signals, all of the 60x processor interface signals are shared by all
60x processors.
Number of
Pins
1
1
1
1
1
1
1
1
1
I/O
O
O
O
O
O
O
I
I
I
Signal Description
Indicates that processor 1 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
Indicates that processor 2 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
Indicates that processor 3 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
Indicates that processor 1 requires mastership of the 60x bus for a
transaction.
Indicates that processor 2 requires mastership of the 60x bus for a
transaction.
Indicates that processor 3 requires mastership of the 60x bus for a
transaction.
mastership of the 60x data bus.
Indicates that processor 2 may, with the proper qualification, assume
mastership of the 60x data bus.
Indicates that processor 3 may, with the proper qualification, assume
mastership of the 60x data bus.
Indicates that processor 1 may, with the proper qualification, assume
2102C–HIREL–01/05