dp83220 National Semiconductor Corporation, dp83220 Datasheet - Page 3

• Manufacturer Part Number: dp83220
• Description: Cdl Twisted Pair Fddi Transceiver Device
• Manufacturer: National Semiconductor Corporation

3 0 Pin Definitions
V
patible circuitry The Transceiver operates from a single
GND (14 22) Return path for the 100K ECL compatible cir-
cuitry power supply
RXV
receive circuitry This power supply is intentionally separat-
ed from others to eliminate receive errors due to coupled
supply noise
RXGND (3 28) Return path for the receive power supply
circuitry This Power supply return is intentionally separated
from others to eliminate receive errors due to coupled sup-
ply noise
TXV
portion of the transmit circuitry This power supply is inten-
tionally separated from the others to prevent supply noise
from coupling to the transmit outputs
TXGND (7 10) Return path for the analog transmit power
supply circuitry This supply return is intentionally separated
from others to prevent supply noise from being coupled to
the transmit outputs
EXTV
cuitry
RXI
nals meeting the input threshold for a given media type are
output through PMID
PMID
used as the source of the receive data for the DP83231
Clock Recover Device (CRD
PMRD
transmit data inputs originating from the DP83251 55 Physi-
cal Layer Device (PLAYER
a
CC
5 V
g
CC
CC
(13 26) Positive power supply for the 100K ECL com-
DC
g
CC
g
(2 1) Balanced differential line receiver inputs Sig-
(5 11) Positive power supply required by the analog
(4 27) Positive power supply for the small signal
(25 24) 100K ECL compatible differential outputs
power supply
(23) Positive power supply for receiver output cir-
(15 16) Differential 100K compatible 4B5B NRZI
See NS Package Number V28A
FIGURE 2 Pin Configuration
Order Number DP83220V
g
28-Pin PLCC
as differential ECL
TM
TM
)
)
TL F 11724 – 3
3
TXO
sated for twisted pair cable
SD
tect outputs indicating that a valid signal is present at the
RXI
DELREF (12) A resistor is connected between this pin and
GND The value of this resistor controls the current into the
delay line calibrator which in turn controls the delay time of
the delay line
TXREF (6) A resistor is connected between this pin and
TXGND The value of this resistor controls the signal ampli-
tude of the TXO
LBEN (19) TTL compatible CMOS Loopback Enable input
pin selects the internal loopback path which effectively
routes the PMRD
MSEL (17) The Media Select input controls the compensa-
tion and output current required to drive to 100 meters of
either STP or DTP media This is a tri-Ievel control pin
When forced to a low voltage STP compensation is select-
ed Forcing a high voltage level will select the DTP compen-
sation mode Forcing a median voltage allows the device to
operate in the transparent mode by deasserting pre-empha-
sis
CDET (18) The Cable Detect input is provided to support
the option of external Cable Detection circuitry With CDET
low the CDL transceiver functions normally When CDET is
high the signal detect output is forced low which inhibits
data reception by the PHY The exception is in the case of
Loop Back where Signal Detect is forced high regardless
g
g
g
(20 21) Differential 100K ECL compatible Signal De-
inputs
(9 8) Differential current driver outputs precompen-
FIGURE 3 System Connection Diagram
g
g
data which drives the twisted pair
data to the PMID
g
differential outputs
TL F 11724 – 4