dp83222 National Semiconductor Corporation, dp83222 Datasheet - Page 6

• Manufacturer Part Number: dp83222
• Description: Cyclone Twisted Pair Fddi Stream Cipher Device
• Manufacturer: National Semiconductor Corporation

3 0 Pin Definitions and Connection Diagrams
TXD
TXC
SCO
DSCO
RXCO
g
g
g
g
g
(18 17)
(13 14)
(19 20)
(27 26)
(24 25)
Differential 100K ECL data inputs This
is the NRZ or NRZI transmit data origi-
nating from the DP83251 5 Physical
Layer
DP83256 7VF or the DP83256VF-AP
Enhanced Physical Layer Devices
(PLAYER
Differential 100K ECL clock inputs
This is the transmit clock generated by
the National Semiconductor Clock
Distribution
DP83257
Enhanced Physical Layer Devices
(PLAYER
Differential 100K ECL data outputs
These outputs present the scrambled
transmit data to the PMD transmitter
Differential 100K ECL outputs These
outputs present the descrambled data
back to the National Semiconductor
DP83251 55 PLAYER the DP83256
7VF
(PLAYER
Differential 100K ECL clock outputs
These outputs supply a time aligned
version of RXC
and hold times relative to DSCO
to
the
or
Devices
a
a
a
)
)
)
National
or
DP83256VF-AP
Device
g
the
(insuring proper set
(PLAYER
FIGURE 6 System Connection Diagrams
DP83256VF-AP
(CDD
Semiconductor
TL F 11885 – 5
TM
TM
devices
)
)
the
the
g
)
6
ENC0 1 (9 8)
CD (10)
SD (12)
(Continued)
DP83251 55 PLAYER the DP83256
7VF
(PLAYER
descrambled data stream DSCO
TTL compatible inputs These pins
work in conjunction with one another
to select different encoding schemes
or to place the DP83222 device into
transparent mode where no scram-
bling or encoding occurs Refer to Ta-
ble II for details of operation
TTL compatible input data This input
accepts the CD (Clock Detect) signal
from the receive Clock Recovery cir-
cuit if available If CD goes to a logic
low level due to insufficient data edg-
es for clock recovery the Stream Ci-
pher will switch to Sample mode in or-
der to restart the synchronization pro-
cess
Single-ended ECL data input This in-
put accepts the SD
PMD If SD goes to a logic low level
due to loss of signal from the media
the DP83222 will switch to Sample
mode in order to restart the synchroni-
zation process
or
a
) for clocking-in the final
DP83256VF-AP
a
signal from the
TL F 11885 – 6
devices
g