dp83241 National Semiconductor Corporation, dp83241 Datasheet - Page 6

• Manufacturer Part Number: dp83241
• Description: Cdd Device Fddi Clock Distribution Device
• Manufacturer: National Semiconductor Corporation

VCO RST
TXC
TXC
TBC
TBC
LBC1 thru 5
LSC
PHASE SEL
3 0 Pin Descriptions
Symbol
b
a
a
b
23 22 21
25 24
Pin
No
27
11
26
20
19
3
2
I O
O
O
O
O
I
I
VCO Reset TTL compatible input used to reset the internal VCO on system power up This input
stops the VCO from oscillating when at a logic HI level thereby reinitializing each of the gates in
the ring oscillator
Transmit Clock 100K ECL compatible differential outputs for use at 125 MHz as the fiber
medium Transmit Clock (TXC) source for the PLAYER device
Transmit Byte Clock 100K ECL compatible differential outputs for use at 12 5 MHz as a load
strobe or transmit byte clock by the PLAYER device to convert byte wide data to serial format for
fiber medium transmission These outputs are positioned to transition on the falling edge of the
TXC
coherent with the TTL LBC1 output but the phase transition occurs approximately 10 ns earlier
Local Byte Clocks TTL compatible local byte clock outputs which are phase locked to crystal
oscillator reference signals These outputs have a 50% duty cycle waveform at 12 5 MHz The
PHASE SEL input determines whether the five phase outputs are phase offset by 8 ns or 16 ns
Local Symbol Clock TTL compatible 25 MHz output for driving the BMAC device This output’s
negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and 60%
LOW duty cycle
Phase Select TTL compatible input used to select either a 8 ns or 16 ns phase offset between
the 5 local byte clocks The LBC’s are phase offset 8 ns apart when PHASE SEL is at a logic LOW
level and 16 ns apart when at a logic HI level
(Continued)
a
clock output to provide the maximum setup and hold margin They are also phase
6
Description