km681002a Samsung Semiconductor, Inc., km681002a Datasheet
km681002a
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km681002a Summary of contents
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... KM681002A, KM681002AI Document Title 128Kx8 High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Range. Revision History Rev. No. History Rev. 0.0 Initial release with Preliminary. Rev. 1.0 Release to final Data Sheet. 1.1. Delete Preliminary Rev. 2.0 Update D.C parameters. 2.1. Update D.C parameters Items ...
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... The KM681002A is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung s advanced CMOS process and designed for high-speed circuit technology ...
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... KM681002A, KM681002AI ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... KM681002A, KM681002AI AC CHARACTERISTICS ( TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads NOTE : The above test conditions are also applied at industrial temperature range. Output Loads(A) D OUT 255 READ CYCLE ...
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... KM681002A, KM681002AI WRITE CYCLE Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z NOTE : The above parameters are also guaranteed at industrial temperature range ...
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... KM681002A, KM681002AI NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
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... KM681002A, KM681002AI TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low A write ends at the earliest transition CS going high or WE going high ...
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... KM681002A, KM681002AI PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 32-TSOP2-400F #32 #1 21.35 MAX 0.841 20.95 0.825 0.004 0.95 0. 0.10 0.037 0.016 0.004 #17 #16 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( 0.051 ( +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 #17 11.76 0.20 0.463 0.008 #16 0.10 1.00 1.20 0.10 0.039 0.004 0.047 1.27 0.05 MIN 0.050 0.002 - 8 - PRELIMINARY CMOS SRAM Units:millimeters/Inches 9 ...
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... KM681002A, KM681002AI PACKAGE DIMENSIONS CMOS SRAM - 9 - PRELIMINARY Rev 4.0 Ferruary 1998 ...