lm4549a National Semiconductor Corporation, lm4549a Datasheet - Page 20

• Manufacturer Part Number: lm4549a
• Description: Ac ?97 Rev 2.1 Multi-channel Audio Codec With Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

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AC Link Serial Interface Protocol
SDATA_IN: Slot 1 – Status Address / Slot Request Bits
This slot echoes (in bits 18 – 12) the 7-bit address of the
codec control/status register received from the controller as
part of a read-request in the previous frame. If no read-
request was received, the codec stuffs these bits with zeros.
Bits 11, 10 are Slot Request bits that support the Variable
Rate Audio (VRA) capabilities of the LM4549A. For all codec
Primary and Secondary modes, the left and right channels of
the DAC take PCM data from slots 3 and 4 in the Output
Frame respectively. The codec uses bits 11 and 10 to re-
quest DAC data from these two slots. If bits 11 and 10 are set
to 0, the controller should respond with valid PCM data in
slots 3 and 4 of the next Output Frame. If bits 11 and 10 are
set to 1, the controller should not send data.
The codec has full control of the slot request bits. By default,
data is requested in every frame, corresponding to a sample
rate equal to the frame rate (SYNC frequency) – 48 kHz
when XTAL_IN = 24.576 MHz. To send samples at a rate
below the frame rate, a controller should set VRA = 1 (bit 0
in the Extended Audio Control/Status register, 2Ah) and
program the desired rate into the PCM DAC Rate register,
2Ch. Both DAC channels operate at the same sample rate.
Values for common sample rates are given in the Register
Description section (Sample Rate Control Registers, 2Ch,
32h) but any rate between 4 kHz and 48 kHz (to a resolution
of 1 Hz) is supported. Slot Requests from the LM4549A are
issued completely deterministically. For example if a sample
rate of 8000 Hz is programmed into 2Ch then the LM4549A
will always issue a slot request in every sixth frame. A
frequency of 9600 Hz will result in a request every fifth frame
while a frequency of 8800 Hz will cause slot requests to be
spaced alternately five and six frames apart. This determin-
ism makes it easy to plan task scheduling on a system
controller and simplifies application software development.
The LM4549A will ignore data in Output Frame slots that do
not follow an Input Frame with a Slot Request. For example,
if the LM4549A is expecting data at a 8000 Hz rate yet the
AC ’97 Digital Audio Controller continues to send data at
48000 Hz, then only those one-in-six audio samples that
follow a Slot Request will be used by the DAC. The rest will
be discarded.
Bits 9 – 2 are request bits for slots not used by the LM4549A
and are stuffed with zeros. Bits 1 and 0 are reserved and are
also stuffed with zeros.
(Continued)
Bit
15
14
13
12
11
Codec Ready
Description
Slot 1 data
Slot 2 data
Slot 3 data
Slot 4 data
valid
valid
valid
valid
Bit
SLOT 0, INPUT FRAME
1 = AC Link Interface Ready
1 = Valid Status Address or
1 = Valid Status Data
1 = Valid PCM Data
1 = Valid PCM Data
Slot Request
(Left ADC)
(Right ADC)
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SDATA_IN: Slot 2 – Status Data
This slot returns 16-bit status data read from a codec control/
status register. The codec sends the data in the frame fol-
lowing a read-request by the controller (bit 15, slot 1 of the
Output Frame). If no read-request was made in the previous
frame the codec will stuff this slot with zeros.
SDATA_IN: Slot 3 – PCM Record Left Channel
This slot contains sampled data from the left channel of the
stereo ADC. The signal to be digitized is selected using the
Record Select register (1Ah) and subsequently routed
through the Record Select Mux and the Record Gain ampli-
fier to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is
transmitted in an MSB justified format. The remaining 2
LSBs are stuffed with zeros.
18:12
Bits
Bits
19:4
Bits
19:2
9:2
1,0
3:0
1:0
19
11
10
Status Register
Slot 3 Request
Slot 4 Request
(For right DAC
(For left DAC
PCM Record
Left Channel
Request bits
Description
Unused Slot
Description
Description
Status Data
PCM data)
PCM data)
Reserved
Reserved
Reserved
Reserved
Index
data
bit
bit
SLOT 1, INPUT FRAME
SLOT 2, INPUT FRAME
SLOT 3, INPUT FRAME
Stuffed with "0" by LM4549A
Echo of the requested Status
Register address.
Stuffed with "0"s by LM4549A
Stuffed with "0"s by LM4549A
Data read from a codec
control/status register.
Stuffed with “0”s if no
read-request in previous frame.
Stuffed with "0"s by LM4549A
18-bit PCM sample from left
ADC
Stuffed with "0"s by LM4549A
0 = Controller should send
1 = Controller should not
0 = Controller should send
1 = Controller should not
valid data in Slot 3 of the
next Output Frame.
send Slot 3 data.
valid data in Slot 4 of the
next Output Frame.
send Slot 4 data.
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