lm4546a National Semiconductor Corporation, lm4546a Datasheet - Page 24

• Manufacturer Part Number: lm4546a
• Description: Ac ?97 Rev 2 Multi-channel Audio Codec With Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

www.national.com
Low Power Modes
Improving System Performance
The audio codec is capable of dynamic range performance
in excess of 90 db., but the user must pay careful attention to
several factors to achieve this. A primary consideration is
keeping analog and digital grounds separate, and connect-
ing them together in only one place. Some designers show
the connection as a zero ohm resistor, which allows naming
the nets separately. Although it is possible to use a two layer
board, it is recommended that a minimum of four layers be
used, with the two inside layers being analog ground and
digital ground. If EMI is a system consideration, then as
many as eight layers have been successfully used. The 12
and 25 MHz. clocks can have significant harmonic content
depending on the rise and fall times. With the exception of
the digital VDD pins, (covered later) bypass capacitors
should be very close to the package. The analog VDD pins
should be supplied from a separate regulator to reduce
noise. By operating the digital portion on 3.3V instead of 5V,
an additional 0.5-0.7 db improvement can be obtained.
Depending on power supply layout, routing, and capacitor
ESR, a device instability can occur, resulting in increased
noise on the outputs. This can be eliminated by adding an
inductor in the digital supply line between the supply bypass
capacitors and the DVDD pins, which increases the high
frequency impedance of the supply as seen by the part. This
“current starving” technique slows down internal rise and fall
times, which will improve the signal to noise ratio, especially
at low temperatures. In addition, the EMI radiated from the
board is also reduced.
Multiple Codecs
EXTENDED AC LINK
Up to four codecs can be supported on the extended AC
Link. These multiple codec implementations should run off a
common BIT_CLK generated by the Primary Codec. All
codecs share the AC ’97 Digital Controller output signals,
SYNC, SDATA_OUT, and RESET#. Each codec, however,
supplies its own SDATA_IN signal back to the controller, with
the result that the controller requires one dedicated input pin
per codec (Figure 9).
(Continued)
FIGURE 8. AC Link Powerdown Timing
24
By definition there can be one Primary Codec and up to
three Secondary Codecs on an extended AC Link. The
Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00
while Secondary Codecs take identities equal to 01, 10 or
11. The Codec Identity is used as a chip select function. This
allows the Command and Status registers in any of the
codecs to be individually addressed although the access
mechanism for Secondary Codecs differs slightly from that
for a Primary.
The Identity control pins, ID1#, ID0# (pins 46 and 45) are
internally pulled up to DV
configured as ’Primary’ either by leaving ID1#, ID0# open
(NC) or by strapping them externally to DV
ply).
The difference between Primary and Secondary codec
modes is in their timing source and in the Tag Bit handling in
Output Frames for Command/Status register access. For a
timing source, a Primary codec divides down by 2 the fre-
quency of the signal on XTAL_IN and also generates this as
the BIT_CLK output for the use of the controller and any
Secondary codecs. Secondary codecs use BIT_CLK as an
input and as their timing source and do not use XTAL_IN or
XTAL_OUT. The use of Tag Bits is described below.
SECONDARY CODEC REGISTER ACCESS
For Secondary Codec access, the controller must set the tag
bits for Command Address and Data in the Output Frame as
invalid (i.e. equal to 0). The Command Address and Data tag
bits are in slot 0, bits 14 and 13 and Output Frames are
those in the SDATA_OUT signal from controller to codec.
The controller must also place the non-zero value (01, 10, or
11) corresponding to the Identity (ID1, ID0) of the target
Secondary Codec into the Codec ID field (slot 0, bits 1 and 0)
in that same Output Frame. The value set in the Codec ID
field determines which of the three possible Secondary Co-
decs is accessed. Unlike a Primary Codec, a Secondary
Codec will disregard the Command Address and Data tag
bits when there is a match between the 2-bit Codec ID value
(slot 0, bits 1 and 0) and the Codec Identity (ID1, ID0).
Instead it uses the Codec-ID/Identity match to indicate that
the Command Address in slot 1 and (if a “write”) the Com-
mand Data in slot 2 are valid.
DD
. The Codec may therefore be
20030809
DD
(Digital Sup-