tp3094 National Semiconductor Corporation, tp3094 Datasheet
tp3094
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tp3094 Summary of contents
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... TP3094 COMBO Quad PCM Codec/Filter General Description The TP3094 is a monolithic PCM Codec and Fil- ter device implemented using a digital signal pro- cessing architecture. It provides four voice channels, combining transmit bandpass and re- ceive low pass channel filters with companding A- law or m-law PCM encoders and decoders. The device is fabricated using National’ ...
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Simplified Block Diagram GXO0 VXI0- - ADC + VRO0 DAC GXO1 - VXI1- ADC + VRO1 DAC GXO2 VXI2- - ADC + VRO2 DAC GXO3 VXI3- - ADC + VRO3 DAC Digital Signal Processor FIGURE 1. Simplified block diagram 2 ...
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... In 32-bit mode these pins become outputs and generate a frame sync signal with the last bit of the 32-bit stream, in order to allow to cascade an- other TP3094 in 32-bit mode. FSX1 is the Trans- mit Frame output and FSR1 is the Receive Frame output. FSX2,FSX3, FSR2,FSR3 (inputs) Transmit and Receive Frame synchronization in- puts for channel 2 and 3 ...
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... PCM bus. Its value can be either 8.192MHz, 4.096MHz, 2.048MHz or 1.536/ 1.544MHz, and it is automatically selected inter- nally. The TP3094 handles the conversion be- tween the analog signals on the subscriber line and the PCM data samples on a PCM highway. ...
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When both the transmit and receive frame sync of a channel are missing the channel will go into Power Down Mode (if only one of them is missing the channel will not go into Power Down). A max- imum of ...
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... FSX1 and FSR1 become the frame signal carry-out signals, providing a single- bit-long frame pulse during the last bit of the 32- bit stream and allowing another TP3094 to be connected in 32-bit mode. In case any channel is powered down (through the PDN pin) during its assigned time slot the DX pin will be set in tristate and the DR signal will be ignored ...
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Functional Description (continued) bypassing the low frequency filter. Test Modes Normal Operation Single Channel Digital Loopback Single Channel Analog Loopback Single Channel DC Conversion 4 Channels Digital Loopback 4 Channels Analog Loopback 4 Channels DC Conversion Invalid States Where A0, ...
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Timing Diagrams MCLK FSX3 or FSR3 FSX2 or FSR2 FSX0 or FSR0 D7 CH3 CH3 D0 DR TSX FIGURE 2. Timing diagram for PCM Interface, 8-bit mode (Long Frame Sync MCLK TSX t DBTS MCLK ...
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Timing Diagrams (continued) MCLK FSX3 or FSR3 FSX2 or FSR2 FSX0 or FSR0 D7 CH3 D0 DX CH3 TSX FIGURE 5. Timing diagram for PCM Interface, 8-bit mode (Short Frame Sync) TSX t DBTS MCLK 1st 2nd ...
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Timing Diagrams (continued) MCLK FSX0 or FSR0 FSX1 or FSR1 D7 CH0 D0 D7 CH1 CH0 D0 D7 CH1 D0 D7 TSX FIGURE 7. Timing diagram for PCM Interface, 32-bit mode TSX t DBTS MCLK ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Dis- tributors for availability and specifications DGND CC Voltage at any digital inputs or outputs Voltage at any analog inputs or outputs Storage ...
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Electrical Characteristics Symbol Parameter Power Dissipation I 0 Power down current (all CC channels down Power up active current CC (all channel active) Amplitude Response Absolute Levels t Virtual decision value max defined per ITU G.711 G Transmit ...
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Electrical Characteristics Symbol Parameter G Receive gain variation RAL with level Note 2: Measure voiceband image signal, stimulus signal level is -25dBm0. Distortion STD Transmit signal to total XP distortion SFD Transmit single fre- X quency distortion STD Receive signal ...
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Electrical Characteristics Symbol Parameter Envelope delay distortion D Transmit delay, absolute XA D Transmit delay, relative Receive delay, absolute RA D Receive delay, relative Noise N Transmit Idle channel XP noise, ...
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Electrical Characteristics Symbol Parameter Crosstalk CT Receive to transmit R-X crosstalk (Intra-channel Crosstalk) CTFE Far end crosstalk with X analog stimulus (Inter- channel crosstalk) CTNE Near end crosstalk with X digital stimulus (Inter- channel crosstalk) CT Transmit to receive X-R ...
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Timing Specifications Symbol Parameter Clock and Data Timing All timing parameters are measured at V 1/t Frequency of MCLK PM DC MCLK Duty Cycle MCLK t Rise time of MCLK RM t Fall time of MCLK FM t Setup time ...
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Applications Information Tip SLIC Ring Tip SLIC Ring Tip SLIC Ring Tip SLIC Ring FIGURE 9. Typical application in a non cascaded mode System Bus +5V Supply AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Zb FSX0 FSR0 VRO0 T PDN0 ...
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... Tip SLIC Ring Tip SLIC Ring Tip SLIC Ring Tip SLIC Ring Tip SLIC Ring Tip SLIC Ring Tip SLIC Ring FIGURE 10. TP3094 in a cascade mode +5V Supply AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Zb FSX0 FSR0 VRO0 T PDN0 GX11 P FSX1 3 VXI1 FSR1 ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specification. 44-Lead Molded Plastic Chip Carrier (PLCC) Order Number TP3094V NS Package Number V44A reasonably expected to result in a significant injury to the user ...