adav801 Analog Devices, Inc., adav801 Datasheet - Page 30

• Manufacturer Part Number: adav801
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV801
INTERFACE CONTROL
The ADAV801 has a dedicated control port to allow access to
the internal registers of the ADAV801. Each of the internal
registers is eight bits wide. Where bits are described as reserved
(RES), these bits should be programmed as zero.
SPI INTERFACE
Control of the ADAV801 is via an SPI-compatible serial port.
The SPI control port is a 4-wire serial control port with one
cycle of data transfer consisting of 16 bits. Figure 53 shows the
format of an SPI write/read of the ADAV801. The transfer of
data is initiated on the falling edge of CLATCH. The data
presented on the first seven CCLKs represents the register
address read/write bit. If this bit is low, the following eight bits
of data are loaded to the register address provided. If this bit is
high, a read operation is indicated. The contents of the register
address are clocked out on the COUT pin on the following eight
CCLKs. For a read operation, the data bits after the read/write
bits are ignored.
CLATCH
COUT
CCLK
CIN
CLATCH
CLATCH
COUT
CIN
CIN
D15
REGISTER
REGISTER
15
D14
14
8 BITS
8 BITS
ADDRESS [6:0]
13
R/W = 0
R/W = 1
12
D9
D9
11
Figure 53. SPI Serial Port Timing Diagram
REGISTER DATA
REGISTER DATA
Figure 55. SPI Block Write Operation
Figure 54. SPI Control Word Format
Figure 56. SPI Block Read Operation
10
8 BITS
8 BITS
D8
D8
9
Rev. A | Page 30 of 60
R/W
8
7
REGISTER + 1 DATA
BLOCK READS AND WRITES
The ADAV801 provides the user with the ability to write to or
read from a block of registers in one continuous operation. In
SPI mode, the CLATCH line should be held low for longer than
the 16 CCLK periods to use the block read/write mode. For a
write operation, once the LSB has been clocked into the
ADAV801 on the 16th CCLK, the register address as specified
by the first seven bits of the write operation is incremented and
the next eight bits are clocked into the next register address.
The read operation is similar. Once the LSB of a read register
operation has been clocked out, the register address is
incremented and the data from the next register is clocked out
on the following eight CCLKs. Figure 55 and Figure 56 show the
timing diagrams for the block write and read operations.
REGISTER + 1 DATA
6
DON’T CARE
8 BITS
8 BITS
5
DATA [7:0]
4
3
2
REGISTER + 2 DATA
REGISTER + 2 DATA
1
8 BITS
8 BITS
0
D0
D0