ADAU1966 AD [Analog Devices], ADAU1966 Datasheet
ADAU1966
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ADAU1966 Summary of contents
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... The ADAU1966 is available in an 80-lead LQFP package. The ADAU1966 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the internal master clock ...
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... ADAU1966 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 5 Digital Input/Output Specifications........................................... 6 Power Supply Specifications........................................................ 6 Digital Filters ................................................................................. 7 Timing Specifications .................................................................. 7 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ...
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... kHz, −60 dB input 0 dBFS Two channels running, −1 dBFS 16 channels running, −1 dBFS AVDDx = 5.0 V TS_REF pin, AVDDx = 5 pin, AVDDx = 5 pin, AVDDx = 5.0 V VSUPPLY pin VSENSE pin Rev Page ADAU1966 Min Typ Max Unit 105 115.5 dB 108 118 dB − ...
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... ADAU1966 Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 5 V, DVDD = 2 ambient temperature ( 105°C, unless otherwise noted. A Table 2. Parameter DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) Total Harmonic Distortion + Noise Full-Scale Differential Output Voltage ...
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... kHz, −60 dB input 0 dBFS Two channels running Eight channels running AVDDx = 3.3 V TS_REF pin, AVDDx = 3 pin, AVDDx = 3 pin, AVDDx = 3.3 V VSUPPLY pin VSENSE pin Min Typ Max 6 5.2 7.5 to 8.5 12 Rev Page ADAU1966 Typ Max Unit 1.50 V 1.50 1. 5.5 V 2.50 2.59 V Min Typ Max ...
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... ADAU1966 DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < T < +105°C, IOVDD = 5.0 V and 3.3 V ± 10%. A Table 6. Parameter High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Input Capacitance POWER SUPPLY SPECIFICATIONS Table 7 ...
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... CCLK CCP CCP CDATA setup, time to CCLK rising CDATA hold, time from CCLK rising CLATCH setup, time to CCLK rising CLATCH hold, time from CCLK falling CLATCH high, not shown in Figure 14 Rev Page ADAU1966 Min Typ Max Unit 22 kHz S 35 kHz ...
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... ADAU1966 Parameter t COE t COD t COH t COTS SCL t SCLL t SCLH t SCS t SCH t SSH BFT DAC SERIAL PORT t DBH t DBL t DLS t DLH t DLS t DDS t DDH SDA SCL Description COUT enable from CCLK falling COUT delay from CCLK falling ...
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... V to +5.5 V −0 +3.6 V Table 11. Thermal Resistance −0 +3.6 V Package Type −0 +6.0 V 80-Lead LQFP ±20 mA –0 AVDD + 0.3 V ESD CAUTION −0 DVDD + 0.3 V −40°C to +125°C −65°C to +150°C Rev Page ADAU1966 repre- JC θ θ Unit JA JC 42.3 10.0 °C/W ...
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... DVDD 21, 26, 30, 40 GND DGND PIN 1 INDICATOR ADAU1966 TOP VIEW (Not to Scale Figure 3. Pin Configuration Description DAC Bias 3. AC couple with 470 nF to AGND3. DAC Bias 4. AC couple with 470 nF to AVDD3. ...
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... Mode section and Table 15). Control Chip Select (SPI) (Low Active)/Address 0 (I Standalone Mode section and Table 15). Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45, Pin 31, and Pin 32 (high active, see Table 15 and Table 16). Power-Up/Reset (Low Active). ...
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... ADAU1966 1 Pin No. Type Mnemonic 71 O DAC8N 72 O DAC9P 73 O DAC9N 74 O DAC10P 75 O DAC10N 76 O DAC11P 77 O DAC11N 78 O DAC12P 79 O DAC12N 80 GND AGND3 input output, I/O = input/output, PWR = power, GND = ground. Description DAC8 Negative Output. DAC9 Positive Output. DAC9 Negative Output. ...
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... Figure 5. DAC Stop-Band Filter Response, 48 kHz 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0.35 0.40 0.45 0. –10 –20 –30 –40 –50 –60 –70 –80 –90 0.7 0.8 0.9 1.0 –100 Rev Page ADAU1966 0.05 0.10 0.15 0.20 0.25 0.30 f FREQUENCY (FACTORED Figure 6. DAC Pass-Band Filter Response, 96 kHz 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 f FREQUENCY (FACTORED Figure 7. DAC Stop-Band Filter Response, 96 kHz 0.35 0.40 0.9 1.0 ...
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... ADAU1966 APPLICATION CIRCUITS Typical application circuits are shown in Figure 8 to Figure 11. Recommended loop filters for DLRCLK and MCLKI/XTALI modes of the PLL reference are shown in Figure 8. Output filters for the DAC outputs are shown in Figure 9 and Figure 10, and an external regulator circuit is shown in Figure 11. ...
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... The clock functionality of SA_MODE is described in the Standalone Mode section. In program mode, the default for the ADAU1966 is for the MCLKO pin to feed a buffered output of the MCLKI signal. The default for the DLRCLK and DBCLK ports is slave mode; the DAC must be driven with a coherent set of MCLK, LRCLK, and BCLK signals to function ...
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... If the internal PLL is not used best to use an independ- ent crystal oscillator to generate the master clock. If the ADAU1966 used in direct MCLK mode, the PLL can be powered down in the PDN_THRMSENS_CTRL_1 regis- ter. For direct MCLK mode, a 512 × f ...
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... R/W bit. The device address consists of an internal built-in address (0x04) and two address pins, ADDR1 and ADDR0. The two address bits allow four ADAU1966 devices to be used in a system. Initiating a write operation to the ADAU1966 involves sending a start condition and then sending the device address with the R /W bit set low ...
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... Chip Address Data- Word Rev Page FRAME 2 REGISTER ADDRESS BYTE ACK. BY ADAU1966 (AS) FRAME 3 DATA BYTE TO ADAU1966 ADAU1966 (AS) FRAME 2 REGISTER ADDRESS BYTE ACK. BY MASTER (AM) FRAME 4 REGISTER DATA AS ...
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... ADAU1966 register address, and the third byte is the data. POWER SUPPLY AND VOLTAGE REFERENCE The ADAU1966 is designed for 3 analog and 2.5 V digital supplies. To minimize noise pickup, the power supply pins should be bypassed with 100 nF ceramic chip capacitors placed as close to the pins as possible. A bulk aluminum electrolytic capacitor of at least 22 μ ...
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... ADAU1966 TEMPERATURE SENSOR The ADAU1966 has an on-board temperature sensor that allows the user to read the temperature of the silicon inside the part. The temperature sensor readout has a range of −60°C to +140°C in 1°C steps. The PDN_THRMSENS_CTRL_1 register controls the settings of the sensor. The temperature sensor is powered on by default and can be shut off by setting the TS_PDN[2] bit PDN_THRMSENS_CTRL_1 ...
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... Not used Not Used Not used Not used Not used Not used Not used TDM frame sync in/ TDM frame sync in/ TDM frame sync out TDM frame sync out TDM DBCLK in/TDM TDM DBCLK in/ DBCLK out TDM DBCLK out 96 kHz 48 kHz ADAU1966 ...
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... MSB DSDATAx (Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission) To relax the requirement for the setup time of the ADAU1966 in cases of high speed TDM data transmission, the ADAU1966 can latch in the data using the falling edge of DBCLK; see the BCLK_EDGE bit in the DAC_CTRL1 register. This effectively dedicates the entire BCLK period to the setup time ...
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... REGISTER SUMMARY Table 24. ADAU1966 Register Summary Reg Name Bits Bit 7 0x00 PLL_CLK_CTRL0 [7:0] 0x01 PLL_CLK_CTRL1 [7:0] LOPWR_MODE 0x02 PDN_THRMSENS_CTRL_1 [7:0] THRM_RATE 0x03 PDN_CTRL2 [7:0] DAC08_PDN 0x04 PDN_CTRL3 [7:0] DAC16_PDN 0x05 THRM_TEMP_STAT [7:0] 0x06 DAC_CTRL0 [7:0] SDATA_FMT 0x07 DAC_CTRL1 [7:0] BCLK_GEN 0x08 DAC_CTRL2 [7:0] RESERVED 0x09 DAC_MUTE1 [7:0] DAC08_MUTE DAC07_MUTE DAC06_MUTE DAC05_MUTE DAC04_MUTE DAC03_MUTE ...
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... ADAU1966 REGISTER DETAILS PLL AND CLOCK CONTROL 0 REGISTER Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0 Table 25. Bit Descriptions for PLL_CLK_CTRL0 Bits Bit Name Settings [7:6] PLLIN [5:4] XTAL_SET SOFT_RST [2:1] MCS PUP Description PLL Input Select. Selects between MCLKI/XTALI or DLRCLK as the input to the PLL ...
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... PLL Lock Indicator. 0 PLL Not Locked 1 PLL Locked Internal Voltage Reference Enable. The internal voltage reference powers the common mode for the ADAU1966. Disabling this bit allows the user to drive the CM pin with an outside voltage source. 0 Disabled 1 Enabled DAC Clock Select. Selects between PLL or Direct MCLK mode. ...
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... ADAU1966 BLOCK POWER-DOWN AND THERMAL SENSOR CONTROL 1 REGISTER Address: 0x02, Reset: 0xA0, Name: PDN_THRMSENS_CTRL_1 Table 27. Bit Descriptions for PDN_THRMSENS_CTRL_1 Bits Bit Name Settings [7:6] THRM_RATE THRM_MODE 4 THRM_GO 2 TS_PDN 1 PLL_PDN 0 VREG_PDN Description Conversion Time Interval. When THERM_MODE = 0, the THERM_RATE bits control the time interval between temperature conversions. ...
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... Normal Operation 1 Power-Down Channel 5 Channel 4 Power-Down. 0 Normal Operation 1 Power-Down Channel 4 Channel 3 Power-Down. 0 Normal Operation 1 Power-Down Channel 2 Channel 2 Power-Down. 0 Normal Operation 1 Power-Down Channel 2 Channel 1 Power-Down. 0 Normal Operation 1 Power-Down Channel 1 Rev Page ADAU1966 Reset Access 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ...
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... ADAU1966 POWER-DOWN CONTROL 3 REGISTER Address: 0x04, Reset: 0x00, Name: PDN_CTRL3 Table 29. Bit Descriptions for PDN_CTRL3 Bits Bit Name Settings 7 DAC16_PDN 6 DAC15_PDN 5 DAC14_PDN 4 DAC13_PDN 3 DAC12_PDN 2 DAC11_PDN 1 DAC10_PDN 0 DAC09_PDN Description Channel 16 Power-Down. 0 Normal Operation 1 Power-Down Channel 16 Channel 15 Power-Down. 0 Normal Operation 1 Power-Down Channel 15 Channel 14 Power-Down. ...
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... TEMP value into decimal form; then subtract 60 from this decimal conversion. The result is the temperature in degrees Celsius. Table 30. Bit Descriptions for THRM_TEMP_STAT Bits Bit Name Settings [7:0] TEMP Description Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step size. To convert TEMP code to temperature, use the equation (TEMP − 60). Rev Page ADAU1966 Reset Access 0x00 R ...
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... ADAU1966 DAC CONTROL 0 REGISTER Address: 0x06, Reset: 0x01, Name: DAC_CTRL0 B7 [7:6] SDATA_FMT SDATA Format 2 00: I S—1-BCLK Cycle Delay 01: Left-Justified—0-BCLK Cycle Delay 10: Right-Justified 24-bit Data— 8-BCLK Cycle Delay 11: Right-Justified 16-bit Data— 16-BCLK Cycle Delay [5:3] SAI Serial Audio Interface ...
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... SAI_MSB 2 BCLK_RATE 1 BCLK_EDGE 0 SAI_MS Description DBCLK Generation. When the PLL is locked to DLRCLK possible to run the ADAU1966 without an external DBCLK. 0 Normal Operation—DBCLK 1 Internal DBCLK Generation DLRCLK Mode Select. Only Valid for TDM modes. 0 50% Duty Cycle DLRCLK 1 Pulse Mode DLRCLK Polarity. Allows the swapping of data between channels. ...
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... ADAU1966 DAC CONTROL 2 REGISTER Address: 0x08, Reset: 0x06, Name: DAC_CTRL2 Table 33. Bit Descriptions for DAC_CTRL2 Bits Bit Name Settings [6:5] VREG_CTRL BCLK_TDMC 3 DAC_POL 2 AUTO_MUTE_EN 1 DAC_OSR 0 DE_EMP_EN Description Voltage Regulator Control. Select the Regulator Output Voltage. Regulator Out = 2.5 V Regulator Out = 2.75 V Regulator Out = 3.0 V Regulator Out = 3 ...
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... DAC4 Normal Operation 1 DAC4 Mute DAC3 Soft Mute. 0 DAC3 Normal Operation 1 DAC3 Mute DAC2 Soft Mute. 0 DAC2 Normal Operation 1 DAC2 Mute DAC1 Soft Mute. 0 DAC1 Normal Operation 1 DAC1 Mute Rev Page ADAU1966 Reset Access 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ...
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... ADAU1966 DAC INDIVIDUAL CHANNEL MUTES 2 REGISTER Address: 0x0A, Reset: 0x00, Name: DAC_MUTE2 Table 35. Bit Descriptions for DAC_MUTE2 Bits Bit Name Settings 7 DAC16_MUTE 6 DAC15_MUTE 5 DAC14_MUTE 4 DAC13_MUTE 3 DAC12_MUTE 2 DAC11_MUTE 1 DAC10_MUTE 0 DAC09_MUTE Description DAC16 Soft Mute. 0 DAC16 Normal Operation 1 DAC16 Mute DAC15 Soft Mute. ...
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... Description Master Volume Control (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Description DAC Volume Control Channel (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Rev Page ADAU1966 Reset Access 0x00 RW Reset Access 0x00 RW ...
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... ADAU1966 DAC 2 VOLUME CONTROL REGISTER Address: 0x0D, Reset: 0x00, Name: DAC02_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings. Table 38. Bit Descriptions for DAC02_VOL Bits Bit Name Settings [7:0] DAC02_VOL 00000000 00000001 00000010 11111110 ...
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... Description DAC Volume Control Channel (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Description DAC Volume Control Channel (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Rev Page ADAU1966 Reset Access 0x00 RW Reset Access 0x00 RW ...
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... ADAU1966 DAC 6 VOLUME CONTROL REGISTER Address: 0x11, Reset: 0x00, Name: DAC06_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings. Table 42. Bit Descriptions for DAC06_VOL Bits Bit Name Settings [7:0] DAC06_VOL 00000000 00000001 00000010 11111110 ...
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... Description DAC Volume Control Channel (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Description DAC Volume Control Channel (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Rev Page ADAU1966 Reset Access 0x00 RW Reset Access 0x00 RW ...
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... ADAU1966 DAC 10 VOLUME CONTROL REGISTER Address: 0x15, Reset: 0x00, Name: DAC10_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings. Table 46. Bit Descriptions for DAC10_VOL Bits Bit Name Settings [7:0] DAC10_VOL 00000000 00000001 00000010 11111110 ...
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... Description DAC Volume Control Channel 12 (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Description DAC Volume Control Channel 13 (default) −0.375 dB −0.750 dB −95.250 dB −95.625 dB Rev Page ADAU1966 Reset Access 0x00 RW Reset Access 0x00 RW ...
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... ADAU1966 DAC 14 VOLUME CONTROL REGISTER Address: 0x19, Reset: 0x00, Name: DAC14_VOL Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings. Table 50. Bit Descriptions for DAC14_VOL Bits Bit Name Settings [7:0] DAC14_VOL 00000000 00000001 00000010 11111110 ...
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... Output Pad Drive Strength Control. Pad strength is stated for IOVDD = Drive for All Pads Drive for All Pads Common Mode Generation Selection. 0 Fixed 3.3 V AVDD CM Generation 1 Fixed 5 V AVDD CM Generation Rev Page ADAU1966 Reset Access 0x00 RW Reset Access 0x0 RW 0x1 RW ...
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... ADAU1966 DAC POWER ADJUST 1 REGISTER Address: 0x1D, Reset: 0xAA, Name: DAC_POWER1 Table 54. Bit Descriptions for DAC_POWER1 Bits Bit Name Settings [7:6] DAC04_POWER [5:4] DAC03_POWER [3:2] DAC02_POWER [1:0] DAC01_POWER Description DAC Power Control Channel 4. Low Power Lowest Power ...
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... Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 6. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 5. Low Power Lowest Power Best Performance Good Performance Rev Page ADAU1966 Reset Access 0x2 RW 0x2 RW 0x2 RW 0x2 RW ...
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... ADAU1966 DAC POWER ADJUST 3 REGISTER Address: 0x1F, Reset: 0xAA, Name: DAC_POWER3 Table 56. Bit Descriptions for DAC_POWER3 Bits Bit Name Settings [7:6] DAC12_POWER [5:4] DAC11_POWER [3:2] DAC10_POWER [1:0] DAC09_POWER Description DAC Power Control Channel 12. Low Power Lowest Power ...
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... Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 14. Low Power Lowest Power Best Performance Good Performance DAC Power Control Channel 13. Low Power Lowest Power Best Performance Good Performance Rev Page ADAU1966 Reset Access 0x2 RW 0x2 RW 0x2 RW 0x2 RW ...
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... ADAU1966 Table 58. Volume Table Binary Value Volume Attenuation (dB) 00000000 0 00000001 −0.375 00000010 −0.75 00000011 −1.125 00000100 −1.5 00000101 −1.875 00000110 −2.25 00000111 −2.625 00001000 −3 00001001 −3.375 00001010 −3.75 00001011 −4.125 00001100 −4.5 00001101 −4.875 00001110 − ...
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... Rev Page ADAU1966 ...
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... ADAU1966 Binary Value Volume Attenuation (dB) 10111010 −69.75 10111011 −70.125 10111100 −70.5 10111101 −70.875 10111110 −71.25 10111111 −71.625 11000000 −72 11000001 −72.375 11000010 −72.75 11000011 −73.125 11000100 −73.5 11000101 −73.875 11000110 −74.25 11000111 −74.625 11001000 − ...
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... W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADAU1966W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications ...
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... ADAU1966 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09434-0-9/11(0) Rev Page ...