adav803ast-reel7 Analog Devices, Inc., adav803ast-reel7 Datasheet - Page 20

• Manufacturer Part Number: adav803ast-reel7
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV803
The worst-case images can be computed from the zero-order
hold frequency response:
where:
F is the frequency of the worst-case image that would be
2
f
The following worst-case images would appear for f
192 kHz:
Hardware Model
The output rate of the low-pass filter in Figure 30 is the
interpolation rate:
Sampling at a rate of 201.3 GHz is clearly impractical, in
addition to the number of taps required to calculate each
interpolated sample. However, because interpolation by 2
involves zero-stuffing 2
most of the multiplies in the low-pass FIR filter are by zero. A
further reduction can be realized because only one interpolated
sample is taken at the output at the f
convolution needs to be performed per f
2
sufficient to suppress the images caused by the interpolation.
One difficulty with the preceding approach is that the correct
interpolated sample must be selected upon the arrival of f
Because there are 2
arrival of the f
1/201.3 GHz = 4.96 ps. Measuring the f
of 201.3 GHz frequency is clearly impossible; instead, several
coarse measurements of the f
averaged over time.
Another difficulty with the preceding approach is the number
of coefficients required. Because there are 2
tions with a 64-tap FIR filter, there must be 2
coefficients for each tap, which requires a total of 2
cients. To reduce the number of coefficients in ROM, the SRC
stores a small subset of coefficients and performs a high order
interpolation between the stored coefficients.
The preceding approach works when f
when the output sample rate, f
rate, f
the convolution must be scaled. As the input sample rate rises
over the output sample rate, the antialiasing filter’s cutoff
frequency must be lowered because the Nyquist frequency of
the output samples is less than the Nyquist frequency of the
input samples. To move the cutoff frequency of the antialiasing
filter, the coefficients are dynamically altered and the length of
the convolution is increased by a factor of (f
S_INTERP
20
20
× f
convolutions. A 64-tap FIR filter for each f
Maximum Image = sin(π × F/f
Image at f
Image at f
2
S_IN
S_IN
20
= f
× 192,000 kHz = 201.3 GHz
, the ROM starting address, input data, and length of
± f
S_IN
S_IN
× 2
S_OUT
S_INTERP
S_INTERP
/2.
20
.
20
clock must be measured with an accuracy of
possible convolutions per f
− 96 kHz = −125.1 dB
+ 96 kHz = −125.1 dB
20
− 1 samples between each f
S_OUT
S_OUT
clock period are made and
, is less than the input sample
S_INTERP
S_OUT
S_OUT
S_OUT
S_OUT
rate, so only one
)/(π × F/f
20
> f
S_IN
period with a clock
20
period instead of
possible convolu-
S_OUT
S_IN
polyphase
/f
S_OUT
S_OUT
. However,
sample is
S_INTERP
26
S_IN
S_IN
coeffi-
period, the
).
equal to
sample,
)
20
S_OUT
Rev. A | Page 20 of 60
.
This technique is supported by the Fourier transform property
that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of
decimation is limited by the size of the RAM.
SRC Architecture
The architecture of the sample rate converter is shown in
Figure 32. The sample rate converter’s FIFO block adjusts the
left and right input samples and stores them for the FIR filter’s
convolution cycle. The f
to the FIFO block and the ramp input to the digital servo loop.
The ROM stores the coefficients for the FIR filter convolution
and performs a high order interpolation between the stored
coefficients. The sample rate ratio block measures the sample
rate for dynamically altering the ROM coefficients and scaling
of the FIR filter length as well as the input data. The digital
servo loop automatically tracks the f
and provides the RAM and ROM start addresses for the start of
the FIR filter convolution.
The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample rate
converter and the scaling of the input data by the sample rate
ratio before storing the samples in the RAM. The input data is
scaled by the sample rate ratio because, as the FIR filter length
of the convolution increases, so does the amplitude of the
convolution output. To keep the output of the FIR filter from
saturating, the input data is scaled down by multiplying it by
(f
data for muting and unmuting of the SRC.
The RAM in the FIFO is 512 words deep for both left and right
channels. An offset to the write address provided by the f
counter is added to prevent the RAM read pointer from
overlapping the write address. The minimum offset on the SRC
is 16 samples. However, the group delay and mute-in register
can be used to increase this offset.
The number of input samples added to the write pointer of the
FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay
register. This feature is useful in varispeed applications to
prevent the read pointer to the FIFO from running ahead of the
write pointer. When set, Bit 7 of the group delay and mute-in
register soft-mutes the sample rate. Increasing the offset of the
S_OUT
RIGHT DATA IN
COUNTER
LEFT DATA IN
/f
S_IN
f
S_IN
Figure 32. Architecture of the Sample Rate Converter
) when f
f
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f
S_IN
SAMPLE RATE RATIO
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SERVO LOOP
RATE RATIO
S_IN
SAMPLE
< f
DIGITAL
FIFO
S_IN
counter provides the write address
. The FIFO also scales the input
EXTERNAL
S_IN
RATIO
and f
FIR FILTER
ROM A
ROM B
ROM C
ROM D
S_OUT
L/R DATA OUT
sample rates
ORDER
INTERP
HIGH
S_IN