adav803ast-reel7 Analog Devices, Inc., adav803ast-reel7 Datasheet - Page 43

• Manufacturer Part Number: adav803ast-reel7
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

Interrupt Status—Address 0011100 (0x1C)
Table 69. Interrupt Status Register Bit Map
7
SRCError
Table 70. Interrupt Status Register Bit Descriptions
Bit Name
SRCError
TxCSTINT
TxUBINT
TxCSBINT
RxCSDIFF
RxUBINT
RxCSBINT
RxERROR
Interrupt Status Mask—Address 0011101 (0x1D)
Table 71. Interrupt Status Mask Register Bit Map
7
SRCError Mask
Table 72. Interrupt Status Mask Register Bit Descriptions
Bit Name
SRCError Mask
TxCSTINT Mask
TxUBINT Mask
TxCSBINT Mask
RxUBINT Mask
RxCSBINT Mask
RxError Mask
6
TxCSTINT
Description
This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample
rate converter error register. This bit remains high until the interrupt status register is read.
This bit is set if a write to the transmitter channel status buffer was made while transmitter channel status bits were being
copied from the transmitter CS buffer to the S/PDIF transmit buffer.
This bit is set if the S/PDIF transmit buffer is empty. This bit remains high until the interrupt status register is read.
This bit is set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit remains high
until the interrupt status register is read.
This bit is set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit remains
high until read, but does not generate an interrupt.
This bit is set if the receiver user bit buffer has a new block or message. This bit remains high until the interrupt status
register is read.
This bit is set if a new block of channel status is read when RxBCONF3 = 0, or if the channel status has changed when
RxBCONF3 = 1. This bit remains high until the interrupt status register is read.
This bit is set if one of the AES3/S/PDIF receiver interrupts is asserted, and the host should immediately read the receiver
error register. This bit remains high until the interrupt status register is read.
6
TxCSTINT Mask
Description
Masks the SRCError bit from generating an interrupt.
Masks the TxCSTINT bit from generating an interrupt.
Masks the TxUBINT bit from generating an interrupt.
Masks the TxCSBINT bit from generating an interrupt.
Masks the RxUBINT bit from generating an interrupt.
Masks the RxCSBINT bit from generating an interrupt.
Masks the RxError bit from generating an interrupt.
0 = SRCError bit does not generate an interrupt.
1 = SRCError bit generates an interrupt.
0 = TxCSTINT bit does not generate an interrupt.
1 = TxCSTINT bit generates an interrupt.
0 = TxUBINT bit does not generate an interrupt.
1 = TxUBINT bit generates an interrupt.
0 = TxCSBINT bit does not generate an interrupt.
1 = TxCSBINT bit generates an interrupt.
0 = RxUBINT bit does not generate an interrupt.
1 = RxUBINT bit generates an interrupt.
0 = RxCSBINT bit does not generate an interrupt.
1 = RxCSBINT bit generates an interrupt.
0 = RxError bit does not generate an interrupt.
1 = RxError bit generates an interrupt.
5
TxUBINT
5
TxUBINT Mask
4
TxCSBINT
4
TxCSBINT Mask
Rev. A | Page 43 of 60
3
RxCSDIFF
3
Reserved
2
RxUBINT Mask
2
RxUBINT
1
RxCSBINT Mask
1
RxCSBINT
0
RxERROR
ADAV803
0
RxError Mask