adv202 Analog Devices, Inc., adv202 Datasheet
adv202
Available stocks
Related parts for adv202
adv202 Summary of contents
Page 1
... ITU.R-BT1358 (625p) or any video format with a maximum input rate of 65 MSPS for irreversible mode or 40 MSPS for reversible mode Two or more ADV202s can be combined to support full- frame SMPTE274M HDTV (1080i) or SMPTE296M (720p) Flexible asynchronous SRAM-style host interface allows glueless connection to most 16-/32-bit microcontrollers and ASICs 2 ...
Page 2
... Pin Function Descriptions ........................................................ 23 Theory of Operation ...................................................................... 26 Wavelet Engine ........................................................................... 26 Entropy Codecs........................................................................... 26 Embedded Processor System .................................................... 26 Memory System.......................................................................... 26 Internal DMA Engine ................................................................ 26 ADV202 Interface .......................................................................... 27 Video Interface (VDATA Bus).................................................. 27 Host Interface (HDATA Bus) ................................................... 27 Direct and Indirect Registers .................................................... 27 Control Access Registers ........................................................... 27 Pin Configuration and Bus Sizes/Modes ................................ 28 Stage Register .............................................................................. 28 JDATA Mode ...
Page 3
... Changes to Figure 22 ......................................................................18 Deleted SPI Port Timing Section ..................................................18 Added Absolute Maximum Ratings Section ...............................19 Changes to Pin BGA Assignments and Function Descriptions Section .......................................................................20 Changes to ADV202 Interface Section.........................................27 Changes to Table 19 ........................................................................29 Changes to Indirect Registers Section..........................................30 Changes to PLL Section..................................................................31 Changes to Table 23 ........................................................................31 Changes to Video Input Formats Section ....................................32 Changes to Figure 24 ...
Page 4
... ADV202 GENERAL DESCRIPTION (continued from Page 1) The ADV202 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV202 contains a dedicated wavelet transform engine, three entropy codecs, an on-board memory system, and an embedded RISC processor that can provide a complete JPEG2000 compression/decompression solution ...
Page 5
... DD Dynamic Current, Core (JCLK Frequency = 150 MHz) Dynamic Current, Core (JCLK Frequency = 108 MHz) Dynamic Current, Core (JCLK Frequency = 81 MHz) Dynamic Current, I/O Dynamic Current, PLL 1 No clock or I/O activity. 2 ADV202-150 only. INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter Description V High Level Input Voltage IH (3 High Level Input Voltage IH (2 ...
Page 6
... ADV202 CLOCK AND RESET SPECIFICATIONS Table 3. Parameter Description 1 t MCLK Period MCLK t MCLK Width Low MCLKL t MCLK Width High MCLKH t VCLK Period VCLK t VCLK Width Low VCLKL t VCLK Width High VCLKH t RESET Width Low RST 1 For a definition of MCLK, see the PLL section. ...
Page 7
... RCYC ACK t t DRD HZRD VALID Figure 3. Normal Host Mode—Read Operation Rev Page ADV202 Typ Max Unit 1.5 × JCLK 1 + 7.0 ns 15.5 × JCLK + 7.0 ns 1.5 × JCLK + 7.0 ns 15.5 × JCLK + 7 JCLK JCLK JCLK ...
Page 8
... ADV202 NORMAL HOST MODE—WRITE OPERATION Table 5. Parameter Description t (Direct ACK, Direct Registers and FIFO Accesses ACK t (Indirect ACK, Indirect Registers ACK t Data Setup SD t Data Hold HD t Address Setup SA t Address Hold Setup Hold HC t Write Inactive Pulse Width (Minimum Time Until Next WE Pulse) ...
Page 9
... NOT Programmed to a Value of 0000) t DREQRTN DACK HI DACK (EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000) Rev Page Typ Max Unit 15 JCLK cycles 3.5 × JCLK + 7.5 ns JCLK cycles JCLK cycles JCLK cycles ns 2.5 × JCLK + 7.5 ns JCLK cycles 3.5 × JCLK + 7.5 ns JCLK cycles t WEHD WEHD 2 ADV202 2 ...
Page 10
... ADV202 DREQ DREQ DACK t WESU WEFB HDATA Figure 7. Fly-By DMA Mode—Single Write Cycle ( DREQ Pulse Width Is Programmable) FSC0 WE FIFO NOT FULL FSRQ0 HDATA PULSE t DREQ DACK HI DACK WFSRQ Figure 8. DCS DMA Mode—Single Write Access (Rev. 0.1 and Higher) Rev ...
Page 11
... Programmed to a Value of 0000) Rev Page Min Typ Max 1 15 2.5 3.5 × JCLK + 7 2 1.5 2.5 × JCLK + 7.5 ns 2.5 3.5 × JCLK + 7 RDHD 2 t RDHD 2 ADV202 Unit 2 JCLK cycles JCLK cycles JCLK cycles JCLK cycles ns JCLK cycles JCLK cycles ...
Page 12
... ADV202 DREQ DREQ DACK t RDSU RDFB HDATA FCS0 RD FIFO NOT EMPTY FSRQ0 HDATA PULSE t DREQ DACK HI DACK Figure 11. Fly-By DMA Mode—Single Read Cycle ( DREQ Pulse Width Is Programmable) RDFSRQ Figure 12. DCS DMA Mode—Single Read Access (Rev. 0.1 and Higher) Rev ...
Page 13
... DREQRTN t DACKSU (EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000) Rev Page Typ Max 15 3.5 × JCLK + 7 4.5 × JCLK + 7 DREQWAIT DREQWAIT ADV202 Unit JCLK 2 cycles JCLK cycles JCLK cycles JCLK cycles JCLK cycles ...
Page 14
... ADV202 DREQ DACK WEFB HDATA EXTERNAL DMA MODE—FIFO READ, BURST MODE Table 9. Parameter Description 1 DREQ DREQ Pulse Width PULSE DREQ Deassert (DR × PULS = 0) DREQ RTN t DACK to RD Setup DACK Data Valid RD t Data Hold Assert Pulse Width ...
Page 15
... Figure 17. Burst Read Cycle for DREQ / DACK DMA Mode for Assigned DMA Channel (EMOD0/EDMOD1[14:11] Programmed to a Value of 0000) t DREQRTN DREQ DACK t DACKSU RDFB HDATA t RD Figure 18. Burst Read Cycle, Fly-By DMA Mode ( DREQ Pulse Width Is Programmable Rev Page ADV202 t DREQWAIT t DREQWAIT ...
Page 16
... ADV202 STREAMING MODE (JDATA)—FIFO READ/WRITE Table 10. Parameter Description JDATA MCLK to JDATA Valid TD VALID MCLK to VALID Assert/Deassert TD HOLD HOLD Setup to Rising MCLK SU HOLD HOLD Hold from Rising MCLK HD JDATA JDATA Setup to Rising MCLK SU JDATA JDATA Hold from Rising MCLK HD 1 For a definition of JCLK, see the PLL section. ...
Page 17
... Rev Page Min Typ Max SAV SAV SAV HSYNC HD VSYNC HD ADV202 Unit VCLK cycles VCLK cycles VCLK cycles Y Cb ...
Page 18
... ADV202 RAW PIXEL MODE TIMING Table 12. Parameter Description VDATA VCLK to PIXELDATA Valid Delay (PIXELDATA Output) TD VDATA PIXELDATA Setup to Rising VCLK (PIXELDATA Input) SU VDATA PIXELDATA Hold from Rising VCLK (PIXELDATA Input) HD VRDY VCLK to VRDY Valid Delay TD VFRM VFRM Setup to Rising VCLK (VFRAME Input) ...
Page 19
... THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 14. Thermal Resistance Package Type ADV202 (144-Lead) ADV202 (121-Lead) ESD CAUTION Rev Page ADV202 θ θ Unit JA JC 22.5° ...
Page 20
... ADV202 PIN BGA ASSIGNMENTS AND FUNCTION DESCRIPTIONS PIN BGA ASSIGNMENTS Table 15. Pin BGA Assignments for 121-Lead Package Pin. No. Pin Location Pin Description 1 A1 DGND 2 A2 HDATA[ VDD 4 A4 DGND 5 A5 HDATA[ HDATA[ VDATA[ VDD 9 A9 DGND 10 A10 ...
Page 21
... F10 71 F11 72 F12 Rev Page ADV202 Pin Description DGND DGND SCOMM[7] SCOMM[6] SCOMM[5] SCOMM[2] TEST4 RESET DGND MCLK PLLVDD DGND Pin Description HDATA[10] HDATA[9] IOVDD DGND VDD VDD DGND IOVDD VDATA[11] ...
Page 22
... ADV202 Pin No. Pin Location Pin Description 75 G3 HDATA[20 HDATA[19]_VDATA[15 DGND 78 G6 DGND 79 G7 DGND 80 G8 DGND 81 G9 DGND 82 G10 IRQ 83 G11 ACK 84 G12 HDATA[26]_JDATA[ HDATA[25]_JDATA[ HDATA[24]_JDATA[ HDATA[23 DGND 90 H6 DGND ...
Page 23
... ADV202. The interrupt sources are enabled via bits in Register EIRQIE. F12 O Data Request for External DMA Interface. Indicates that the ADV202 is ready to send/receive data to/from the FIFO assigned to DMA Channel 0. O Used in DCS-DMA Mode. Service request from the FIFO assigned to Channel 0 (asynchronous mode). ...
Page 24
... When not used, this pin should be tied low via a 10 kΩ resistor. M4 I/O This pin must be used in multiple chip mode to align the outputs of two or more ADV202s. For details, see the Applications section and AN-796 Application should be tied low via a 10 kΩ resistor LCODE Output in Encode Mode ...
Page 25
... J6, J7, K6, K7, L6 A8, A12, B5, GND Ground. B8, C5, C8, D5 H9, J5 J9, K5, K8, L5, L8, M1 M8, M11, M12 M10 V Positive Supply for PLL. B4, B9, C4, C9, D4, D9, V Positive Supply for I/O. K4, K9, L4, L9 Rev Page ADV202 ...
Page 26
... ADV202 THEORY OF OPERATION The input video or pixel data is passed on to the ADV202’s pixel interface, where samples are de-interleaved and passed on to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. The resulting wavelet coefficients are then written to internal memory. Next, the entropy codecs code the image data so it conforms to the JPEG2000 standard ...
Page 27
... The default bus mode uses the same pins to transfer control, status, and data to and from the ADV202. In this mode, the ADV202 can support 16- and 32-bit control transfers and 8-, 16-, and 32-bit data transfers. The size of these buses can be selected ...
Page 28
... The bus is always an output during compression operations and is an input during decompression. A 2-pin handshake is used to transfer data over this synchro- nous interface. VALID is used to indicate that the ADV202 is ready to provide or accept data and is always an output. HOLD is always an input and is asserted by the host if it cannot accept/ provide data ...
Page 29
... INTERNAL REGISTERS This section describes the internal registers of the ADV202. DIRECT REGISTERS The ADV202 has 16 direct registers, as listed in Table 19. The direct registers are accessed over the ADDR[3:0], HDATA[31:0 and ACK pins. Table 19. Direct Registers Address Name 0x00 PIXEL 0x01 CODE ...
Page 30
... EDMOD0 External DMA Mode Register 0 EDMOD1 External DMA Mode Register 1 FFTHRP FIFO Threshold for Pixel FIFO Reserved Reserved Reserved Reserved FFTHRC FIFO Threshold for CODE FIFO FFTHRA FIFO Threshold for ATTR FIFO Reserved Reserved Rev Page ADV202 User’s Guide. ...
Page 31
... CLKIN Frequency on MCLK 27 MHz 27 MHz 27 MHz 74.25 MHz Description No-Boot Host Mode. ADV202 does not boot, but all internal registers and memory are accessible through normal host I/O operations. For details, see the ADV202 User’s Guide and the SoC Boot Mode. Reserved. ...
Page 32
... Input rate limits for HDATA can be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. Values in brackets refer to the 135 MHz speed grade version of the ADV202. 2 Minimum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate). ...
Page 33
... Table 25. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses Compression Mode 9/7i 9/7i 9/7i 5/3i 5/3i 5/3i 5/3r 5/3r 5/3r Input Format Tile/Precinct Maximum Width Single-component 2048 Two-component 1024 each Three-component 1024 (Y) Single-component 4096 Two-component 2048 (each) Three-component 2048 (Y) Single-component 4096 Two-component 2048 Three-component 1024 Rev Page ADV202 ...
Page 34
... ADV202 JPEG2000 video processor. ENCODE—MULTICHIP MODE Due to the data input rate limitation (see Table 24), an 1080i application requires at least two ADV202s to encode or decode full-resolution 1080i video. In encode mode, the ADV202 accepts Y and CbCr data on separate buses. The input data must be in EAV/SAV format ...
Page 35
... Figure 26. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode In a slave/slave configuration, the common HVF for both ADV202s is generated by an external house sync, and each SCOMM[5] is connected to the same GPIO output on the host. SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be unmasked on both devices to enable multichip mode ...
Page 36
... ADV202 ENCODE/DECODE SDTV VIDEO APPLICATION Figure 27 shows two ADV202 chips using 10-bit CCIR656 in normal host mode. ENCODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] DECODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV202 VDATA[11:2] VCLK MCLK HDATA[31:0] INTR IRQ ADDR[3: ...
Page 37
... ASIC APPLICATION (32-BIT HOST/32-BIT ASIC) Figure 28 shows two ADV202 chips using 10-bit CCIR656 in normal host mode. ASIC DREQ0 DACK0 DATA[31:0] 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ASIC DREQ0 DACK0 DATA[31:0] 31 -BIT HOST CPU DATA[31:0] ADDR[3:0] ADV202 DREQ0 DACK0 VDATA[11:2] VCLK HDATA[31:0] ...
Page 38
... ACK ACK IRQ IRQ DREQ DREQ0 DACK DACK0 DREQ DREQ1 DACK DACK1 74.25MHz MCLK Figure 29. Host Interface—Pixel Interface Mode ADV202 YCrCb JDATA[7:0] VDATA[11:2] HOLD FIELD VALID VSYNC HSYNC VCLK MCLK HDATA[15:0] IRQ IRQ ADDR[3: ...
Page 39
... Dimensions shown in millimeters Rev Page CORNER INDEX AREA 1.31 1.21 1.11 0.20 NOM SEATING COPLANARITY PLANE A1 CORNER INDEX AREA 1.32 1.21 1.11 COPLANARITY 0.20 MAX SEATING PLANE ADV202 ...
Page 40
... ADV202BBC-135 −40°C to +85°C 1 ADV202BBCZ-135 −40°C to +85°C ADV202BBC-150 −40°C to +85°C 1 ADV202BBCZ-150 −40°C to +85°C 1 ADV202BBCZRL-150 −40°C to +85°C ADV202-HD-EB ADV202-ASD-P160- Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...