ucb1500 NXP Semiconductors, ucb1500 Datasheet
ucb1500
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ucb1500 Summary of contents
Page 1
... PCI to AC97 bridge/host controller Rev. 03 — 7 July 2000 1. General description UCB1500 is a PCI-to-AC97 Bridge/Host Controller for modem or audio codecs equipped with the AC-link interface. It integrates a PCI 2.2 interface for communication with the host PC, with built in support for PPMI (PCI Power Management Interface) and wake-up. It also integrates an AC97 Rev. 2.1 host controller for connection two AC-Link codecs, including analog modem front ends such as the Philips UCB1510, and audio codecs ...
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... Description UCB1500 LQFP80 plastic low profile quad flat package, 80 leads; body 12 5. Block diagram handbook, full pagewidth PCI interface Fig 2. UCB1500 block diagram 9397 750 07443 Product specification PPMI (PCI Power Management Interface) Instantly available PC ACPI UCB1500 CONTROLLER DMA ...
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... Type Description I PCI system clock. I PCI system reset, V powered. AUX T/S PCI bus request. T/S PCI bus grant. [1] S/T/S PCI FRAME, input during slave, output during master. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller 60 AD1 59 AD2 AD3 56 AD4 55 AD5 54 AD6 ...
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... S Ground pins. S Auxiliary power. If auxiliary power is not available or not necessary, this pin must be connected Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller powered and can trigger PME. AUX AUX powered. AUX © Philips Electronics N.V. 2000. All rights reserved. powered. ...
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... Functions 0 and 1 (if enabled) in the BIOS POST routine when UCB1500 is used as a motherboard device. • In case UCB1500 is used as a PCI card which BIOS cannot control, the above parameters, together with Function 1 enable, can be changed by the external serial EEPROM. The EEPROM data map is given in ...
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... Function 0 configuration registers UCB1500 supports the PCI configuration cycle to control the UCB1500 access. It sets up the PCI configuration bits and the UCB1500 IO port address. The following table shows the supported PCI registers and their default values. Some of the registers are programmable through the EEPROM interface (See EEPROM section for details). Remark: All registers are read/write, unless specifi ...
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... Always 0, UCB1500 does not generate memory write and invalidate command. Special Cycle Response Always 0, UCB1500 ignores all special cycles. Bus Master Control PCI Master access enable; this bit must be enabled to activate UCB1500 DMA register enable. Memory Space Response Always 0, UCB1500 does not respond to memory space accesses. ...
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... SERR asserted Set to ‘1’ if UCB1500 asserted SERR. Write ‘1' to clear. Received master abort If set, UCB1500 has received master abort during its slave operation. Write ‘1’ to clear. Received target abort If set, UCB1500 has received target abort during its master operation. Write `1' ...
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... This register contains a copy of the Class Code registers. Description EEPROM autoload status If set, EEPROM autoload cycle is in progress. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller Programmable through This register contains a copy of the © Philips Electronics N.V. 2000. All rights reserved. ...
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... EEPROM signature. This bit is for testing only. This register is set to 01h to indicate power This field provides an offset into the function's Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller This register contains a copy of This register contains a copy of © Philips Electronics N.V. 2000. All rights reserved. ...
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... PCI Power Management Interface Specification . These bits can also be overwritten by BIOS via 6Ah, or loaded from an external EEPROM to 010b for compliance with PCI-PM 1.1. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller = 1, bit 15 shall AUX © Philips Electronics N.V. 2000. All rights reserved. ...
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... D2 11b - D3hot If software writes and the corresponding bit register 82 indicates it is not supported, the state change is discarded. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller (V powered: Only PME Status and AUX © Philips Electronics N.V. 2000. All rights reserved. ...
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... Revision EEPROM Status = 00 Test Register = 00 Reserved Subsystem Vendor ID Write = 1131 Next Item Ptr = 00 Capability PMCSR = 0000 (S) Programmable through EEPROM interface, or Programmable through EEPROM interface, or Rev. 03 — 7 July 2000 UCB1500 Address 00h 04h 08h 0Ch 10h 14h-2Bh 2Ch 30h 34h ...
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... Always 0, UCB1500 does not generate memory write and invalidate command. Special Cycle Response Always 0, UCB1500 ignores all special cycles. Bus Master Control PCI Master access enable; this bit must be enabled to activate UCB1500 DMA register enable. Memory Space Response Always 0, UCB1500 does not respond to memory space accesses. ...
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... SERR asserted Set to ‘1’ if UCB1500 asserted SERR. Write ‘1' to clear. Received master abort If set, UCB1500 has received master abort during its slave operation. Write ‘1’ to clear. Received target abort If set, UCB1500 has received target abort during its master operation. Write `1' ...
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... This register contains a copy of the Class Code registers. Description EEPROM autoload status If set, EEPROM autoload cycle is in progress. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller Programmable through This register contains a copy of the © Philips Electronics N.V. 2000. All rights reserved. ...
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... EEPROM signature. This bit is for testing only. This register is set to 01h to indicate power This field provides an offset into the function's Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller This register contains a copy of This register contains a copy of © Philips Electronics N.V. 2000. All rights reserved. ...
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... PCI Power Management Interface Specification . These bits can also be overwritten by BIOS via 6Ah, or loaded from an external EEPROM to 010b for compliance with PCI-PM 1.1. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller = 1, bit 15 shall AUX © Philips Electronics N.V. 2000. All rights reserved. ...
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... D1 10b - D2 11b - D3hot If software writes and the corresponding bit register 82 indicates it is not supported, the state change is discarded. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller powered) AUX © Philips Electronics N.V. 2000. All rights reserved ...
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... Product specification Description Descriptor Table Pointer [15:3] Bits 15-3 of receive DMA #1 Descriptor Table Pointer. 32-bit DTP points to location of descriptor table in local memory. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved AUX ...
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... Upon detecting an overrun condition, UCB1500 will clear the invalid bit of the current descriptor, flush the internal FIFO, and then resume the DMA cycle. UCB1500 keeps track of the number of DMA errors caused by buffer overrun and will generate the auto recovery cycle until the count reaches 15h at which time the DMA cycle is aborted ...
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... Set this bit to 1 initiate DMA#1 receive mode after the receive descriptor tables are setup. HOLD status/acknowledge If this bit is set upon a read access, the UCB1500 is currently in the hold condition result of reading an invalid descriptor entry, and is waiting for an acknowledgment before proceeding. Writing this bit will send a hold acknowledge to the UCB1500 ...
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... Set this bit clear abort status initiated by setting the transmit abort bit. This bit clears the PCI abort and transmit abort condition. This is a write only bit and it automatically goes back to 0 after one clock. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Set this bit to initiate DMA#1 transmit mode after the transmit descriptor tables are ready. HOLD status/acknowledge If this bit is set upon a read access, the UCB1500 is currently in the hold condition result of reading an invalid descriptor entry, and is waiting for an acknowledgment before proceeding. Writing a ‘1’ to this bit will send a hold acknowledge to the UCB1500 ...
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... Description Reserved. Transmit DMA #1 DT index Transmit DMA #1 pointer to the current descriptor being processed in the descriptor table. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Product specification Description Reserved. PCI read retry complete If set, UCB1500 will always complete any read cycle that is being retried by the PCI target even if DMA is aborted. The data returned is then discarded. Recommended setting is 1. Reserved. PCI bus outstanding cycle limit 00 = allow 1 outstanding PCI master read cycle and 1 master write cycle ...
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... When UCB1500 generates an interrupt, first interrupt blocks the subsequent interrupts. Thus, when the interrupt routine acknowledges the interrupt, only the first sequence of interrupt event gets cleared. The UCB1500 would then generate another interrupt to account for the subsequent events, which will then be cleared by the next acknowledge from the interrupt service routine ...
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... Reserved. Counter #0 interrupt Counter #1 interrupt Reserved. Transmit DMA #0 error Receive DMA #0 error Transmit DMA #0 DT done/Hold Receive DMA #0 DT done/Hold Reserved. Receive DMA #0 done Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Reserved. Counter #0 interrupt Counter #1 interrupt Reserved. Transmit DMA #0 error Receive DMA #0 error Transmit DMA #0 DT done/Hold Receive DMA #0 DT done/Hold Reserved. Receive DMA #0 done Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Writing a ‘1’ to this bit will clear and then restart counter #1. Clear counter #1 Writing a ‘1’ to this bit will clear and then restart counter #0. Reserved. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... EEPROM ERROR in the previous cycle EEPROM acknowledge not received. EEPAUTO 1 = Power-up Auto load EEPROM initialization in progress Auto mode EEPROM cycle in progress status Reserved EEPROM in manual mode Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Rate = 48 kHz * Transmit rate / 256 For example, if set to 80h, every other AC97 frame transmitted will contain valid data. 00h = 256 (default mode = 48 kHz) ffh = 255 Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Enables transmit channel #0 DMA output during AC97 slot 4. (Same encoding as bits 15-14.) PCM left channel output slot enable Enables transmit channel #0 DMA output during AC97 slot 3. (Same encoding as bits 15-14.) Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... PCM left channel input slot enable Enables receive channel #0 DMA to store data received on AC97 slot disable 01 = store 16-bits 10 = store 18-bits 11 = store 20-bits Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Handset ADC output slot enable Enables transmit channel #0 DMA to output data to AC97 output slot 11. (Same encoding as in regC1.) Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... This bit is output during AC97 slot 1 bit 19. Reserved. Command register index Register index to use when generating register read/write command to AC97 codec. This data is output during AC97 slot 1, bits[18-12]. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... SDATAOUT and SYNC signals are forced to zero. Warm AC97 Reset Writing a “1” to this register will cause UCB1500 to generate a Warm AC97 reset by driving SYNC HIGH for a minimum Reads to this bit will return a “1” while power- progress. Warm AC97 reset will only occur if BITCLK is inactive for at least 1 audio frame ...
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... Reserved. GPIO_INT interrupt mode Specifies which transition on GPIO_INT will generate the interrupt, if enabled. 100 = level 0 101 = level 1 110 = positive edge 111 = negative edge Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Shutdown AC Link Default = 0. Writing “1” to this register shall cause UCB1500 to disable AC Link signals (SYNC and SDATA_OUT to 0). Writing “0” shall enable normal AC Link operation. Channel #1 Codec Ready status This bit reflects the Codec Ready bit of AC97 Channel #1. ...
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... AC97 channel #1 wake-up event occurred. Write “1” to clear. This status bit is set if a LOW-to-HIGH transition occurs in SDATAIN[1] and AC97 Channel #1 wake-up enable of register d8h is set. Reserved. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Function are invalid, and PME is not generated externally. powered) aux Description Scratch register Sticky, can be used for user-defined functions. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller powered). At power-up, or aux © Philips Electronics N.V. 2000. All rights reserved ...
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... Receive DMA #1 error Reserved. Receive DMA #0 DT done/Hold Receive DMA #1 DT done/Hold Reserved. Receive DMA #0 done Receive DMA #1 done Reserved. Description Reserved. AC97 GPIO_INT occurred Reserved. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... No empty DT entries are allowed. The DT has the continuous physical memory space GigaBytes. 2. The data buffer area pointed by each DT entry must not exceed 64K 1 in size. The data address must be double-word aligned as the UCB1500 fetches 4 bytes at a time. 9397 750 07443 Product specifi ...
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... Invalid entry bit: If set, it means that the current descriptor entry is not a valid entry. For transmission, this means that all the data pointed to by the descriptor has been transmitted. If the UCB1500 reads a descriptor entry with this bit set, it enters the hold condition (see hold condition section). ...
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... Invalid entry bit: If set, it means that the current descriptor entry is not a valid entry. For receive, this means the buffer corresponding to the descriptor is full, and valid data is contained. If the UCB1500 reads a descriptor entry with this bit set, it enters the hold condition (see hold condition section). ...
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... At transmit done interrupt, examine transmit DT index and Byte counter to 9.3.2 Receive algorithm 1. Create a receive DT using the circular queue configuration. 2. Initialize UCB1500 DMA registers (refer to a. Set the transmit DTP Invalid Bit Mask of the DMA channel in use. b. Start transmission, while monitoring transmit done interrupt. ...
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... output slew rate output output slew rate output Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller Min Max Unit 40 +125 0.5 +4.6 V 0.5 +6.0 V Min Typ Max Unit 3.0 3.3 3 ...
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... V > V > 3.1 V. out out ) for 0 V < V < 0.71 V. out Parameter PCICLK cycle time PCICLK HIGH time PCICLK LOW time PCICLK slew rate Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller Typ Max V – 1.4 out ----------------------------- - 0.024 Eqt’n A [1] 142 [2] Eqt’ ...
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... Data out hold time Clock to output Write cycle time Parameter BITCLK period Output delay from rising edge of BITCLK Input setup to falling edge of BITCLK Input hold from falling edge of BITCLK Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller Min Max Unit ...
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... T_high CLK T_fval output delay T_rval output delay T_off tri-state output T_off input PCICLK # RST Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller T_low MBL147 T_su T_h MBL148 T_rst-clk T_rst-off MBL149 © Philips Electronics N.V. 2000. All rights reserved ...
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... Product specification T_high T_hd:dat T_su:sta T_hd:sta (in) T_aa T_hd:sto (out) EEPD ACK Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller T_low T_su:sto T_su:dat T_hd T_wr STOP START condition condition © Philips Electronics N.V. 2000. All rights reserved. MBL150 ...
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... scale (1) ( 0.18 12.1 12.1 14.15 14.15 0.5 1.0 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC EIAJ MS-026 Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller detail (1) ( 0.75 1.45 1.45 7 0.2 0.15 0.1 0.30 1.05 1.05 0 EUROPEAN ISSUE DATE PROJECTION 99-12-27 00-01-19 © ...
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... Product specification parallel to the transport direction of the printed-circuit board; transport direction of the printed-circuit board. Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller © Philips Electronics N.V. 2000. All rights reserved ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 9397 750 07443 Product specification methods [3] , SO, SOJ Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller Soldering method Wave Reflow not suitable suitable [2] ...
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... Minor editorial change (no change to any specification). Supersedes version 24077 UCB1500- July 2000 (9397 750 07301). 02 20000707 853-2201 Upgraded to Product specification. Supersedes initial version UCB1500-01 of 24077 04 Feb 2000 (9397 750 06854). Modifications: • Add footnotes to • Add • ...
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... Rev. 03 — 7 July 2000 UCB1500 PCI to AC97 bridge/host controller Philips Semiconductors assumes © ...
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... United Kingdom: Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: Tel. +381 11 3341 299, Fax. +381 11 3342 553 Internet: http://www.semiconductors.philips.com (SCA70) Rev. 03 — 7 July 2000 UCB1500 © Philips Electronics N.V. 2000. All rights reserved ...
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... AC97 timing . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14 System timing Package outline . . . . . . . . . . . . . . . . . . . . . . . . 52 16 Soldering 16.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.2 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 53 16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 53 16.4 Manual soldering 16.5 Package related soldering information . . . . . . 54 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 55 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 56 19 Definitions Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Printed in the U.S.A UCB1500 PCI to AC97 bridge/host controller ...