ucb1400 NXP Semiconductors, ucb1400 Datasheet - Page 24

• Manufacturer Part Number: ucb1400
• Description: Audio Codec With Touch Screen Controller And Power Management Monitor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09611
Product data
9.3 Loopback mode
9.4 PLL and sample rates
9.5 Power-down modes
The audio codec incorporates a loopback mode, in which codec input path and output
path are connected in series. It is activated when the LPBK bit in the General
Purpose register (0x20) set. The loopback internally connects the digital output from
the decimator of the ADC to the digital input of the Interpolator of the DAC, allowing
for codec testing without the use of the AC Link.
The audio sample rate is derived from the 24.576 MHz crystal clock for 8, 12, 16, 24,
32, and 48 kHz sample rates, and from the built-in PLL for 11.025, 22.05 and
44.1 kHz sample rates. The ADC and DAC can run at independent sample rates and
are controlled by the ADC and DAC Sample Rate registers (0x32 and 0x2C).
The audio input and output paths can be powered down independently; the input path
is powered down when the PR0 bit in the Power-down Control/Status register (0x26)
is set. The output path is disabled when the PR1 bit of the same register is set. This
provides the user the means to reduce the current consumption of UCB1400 if one
part of the audio codec is not used in the application. When both the input and output
paths are disabled, the PR3 bit of the same register can also be set to turn off the
audio reference to further reduce power consumption.
If the Smart Low Power bits (SLP0 and SLP1) are set in the Feature Control/Status
Register 2 (0x6C), the UCB1400 will power down unused blocks in the audio ADC
analog front end and the PLL in a smart way, ensuring the lowest power consumption
in each audio operating mode.
Rev. 02 — 21 June 2002
Audio codec with touch screen controller
and power management monitor
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
UCB1400
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