at83c26 ATMEL Corporation, at83c26 Datasheet - Page 40

• Manufacturer Part Number: at83c26
• Description: Multiple Smart Card Reader Interface With Power Management
• Manufacturer: ATMEL Corporation

Table 20. SC1_CFG3 (Config Byte 3 for SC1)
40
Bit Number
Bit Number
X
6-4
2-0
7
7-5
7
3
AT83C26
Bit Mnemonic
X
6
CKS1[2:0]
DCK[2:0]
Bit Mnemonic
0
X
X
Reset value = 0x 0001 X000
Notes:
X
5
Description
This bit must be always at 0.
DCK is the first level of prescaler factor. CLK signal is divided by the prescaler value and outputs DCCLK
signal. DCCLK is an input for CCLK prescaler.
DCCLK is used for pad management and dectivation sequence.
Card Clock prescaler factor for CCLK1.
CKS1 [2:0] = 1: CCLK1 = DCCLK
CKS1[2:0] = 2: CCLK1 = DCCLK / 2
CKS1[2:0] = 3: CCLK1 = DCCLK / 4
CKS1 [2:0] = 5: CCLK1 = A2 / 2
CKS1[2:0] = 6: CCLK1 = CLK / 2
CKS1 [2:0] = 7: CCLK1 = CLK / 4
DCK[2:0] = 0: prescaler factor equals 1
DCK[2:0] = 1: prescaler factor equals 2
DCK[2:0] = 2: prescaler factor equals 4
DCK[2:0] = 3: prescaler factor equals 6
DCK[2:0] = 4: prescaler factor equals 8
DCK[2:0] = 5: prescaler factor equals 10
DCK[2:0] = 6: prescaler factor equals 12
DCK[2:0] = 7: Reserved
CKS1 [2:0] = 0: CCLK1 = CLK (the maximum frequency on CLK is 24 MHz)
CKS 1[2:0] = 4: CCLK1 = A2
1. When CKS1 value is changed a special logic insures no glitch occurs on the CCLK1 pin and
2. CCLK1 must be stopped with CKSTOP1 bit before switching from CKS1 = (0, 1, 2, 3, 6, 7) to
actual configuration changes can be delayed by half a period to two periods of CCLK1.
CKS1 = (4, 5) or vice versa.
Description
ICCADJA
4
X
3
X
2
X
1
7511D–SCR–02/07
X
0