isp1181b NXP Semiconductors, isp1181b Datasheet - Page 42

• Manufacturer Part Number: isp1181b
• Description: Isp1181b Full-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13958
Product data
Fig 8. Interrupt logic.
interrupt register
interrupt enable
RESUME
IEP0OUT
SUSPND
EP0OUT
IERESM
IESUSP
RESET
register
IEP0IN
IERST
IESOF
IEEOT
EP0IN
IEP14
EP14
SOF
EOT
.. .
.. .
Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the
Interrupt Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the
associated Endpoint Status Register.
Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the
current bus status when reading the Interrupt Register.
SETUP and OUT token interrupts are generated after ISP1181B has acknowledged
the associated data packet. In bulk transfer mode, the ISP1181B will issue interrupts
for every ACK received for an OUT token or transmitted for an IN token.
In isochronous mode, an interrupt is issued upon each packet transaction. The
firmware must take care of timing synchronization with the host. This can be done via
the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt
Enable Register. If a Start-Of-Frame is lost, PSOF interrupts are generated every
1 ms. This allows the firmware to keep data transfer synchronized with the host. After
3 missed SOF events the ISP1181B will enter ‘suspend’ state.
An alternative way of handling isochronous data transfer is to enable both the SOF
and the PSOF interrupts and disable the interrupt for each isochronous endpoint.
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Rev. 02 — 07 December 2004
hardware configuration
device mode
INTENA
INTPOL
register
register
INTLVL
Full-speed USB peripheral controller
GENERATOR
PULSE
1
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
MGS772
INT
ISP1181B
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