isp1561 NXP Semiconductors, isp1561 Datasheet - Page 47

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isp1561

Manufacturer Part Number
isp1561
Description
Hi-speed Universal Serial Bus Pci Host Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
Table 61.
Table 63.
ISP1561_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcControlCurrentED register: bit allocation
HcBulkHeadED register: bit allocation
11.1.10 HcControlCurrentED register (address: content of the base address
11.1.11 HcBulkHeadED register (address: content of the base address register +
R/W
31
23
15
31
R
R
R
R
0
0
0
7
0
0
register + 24h)
The HcControlCurrentED register contains the physical address of the current ED of the
control list. The bit allocation is given in
Table 62.
28h)
This is a 4-byte register, and the bit allocation is given in
the physical address of the first ED of the bulk list.
Bit
31 to 4
3 to 0
R/W
30
22
14
30
R
R
R
R
0
0
0
6
0
0
Symbol
CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving
-
CCED[3:0]
HcControlCurrentED register: bit description
R/W
29
21
13
29
R
R
R
R
0
0
0
5
0
0
Description
the present. The Host Controller must continue processing the list from
where it left off in the last frame. When it reaches the end of the control list,
the Host Controller checks the CLF (Control List Filled) bit of
HcCommandStatus. If set, it copies the content of HcControlHeadED to
HcControlCurrentED and clears the bit. If not set, it does nothing. The
HCD is allowed to modify this register only when the CLE (Control List
Enable) bit of HcControl is cleared. When set, the HCD only reads the
instantaneous value of this register. Initially, this is set to logic 0 to indicate
the end of the control list.
reserved
Rev. 02 — 5 March 2007
R/W
28
20
12
28
R
R
R
R
0
0
0
4
0
0
CCED[27:20]
CCED[19:12]
BHED[27:20]
CCED[11:4]
Table
R/W
27
19
11
27
R
R
R
0
0
0
3
0
0
-
61.
R/W
Table
26
18
10
26
R
R
R
0
0
0
2
0
0
-
HS USB PCI Host Controller
reserved
63. The register contains
R/W
25
17
25
R
R
R
0
0
9
0
1
0
0
-
© NXP B.V. 2007. All rights reserved.
ISP1561
R/W
47 of 103
24
16
24
R
R
R
0
0
8
0
0
0
0
-

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