z85230 ZiLOG Semiconductor, z85230 Datasheet - Page 28

• Manufacturer Part Number: z85230
• Description: Enhanced Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

Bit
Position
7
6
5
4
3
2
1
0
Table 4. Write Register 7 Prime (WR7’)
PS005303-0907
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Write Register 7 PRIME (WR7’)
W
W
W
W
W
W
W
W
By resetting WR7’ bit 3 to 0, applications which have a long latency to interrupts can gen-
erate the request to read data from the FIFO when one byte is available. The application
can then test the Receive Character Available bit to determine if more data is available.
By setting WR7’ bit 3 to 0, the ESCC can issue an interrupt when the receive FIFO is half
full (4 bytes available), allowing the frequency of interrupts to be reduced. If WR7’ bit 3 is
1, the Receive Character Available interrupt is generated when there are four bytes avail-
able. If the ISR reads four bytes during each routine, the frequency of interrupts is
reduced.
If WR7’ bit 3 is 1 and Receive Interrupt on All Characters and Special Conditions is
enabled, the receive character available interrupt is generated when four characters are
available. However, when a character is detected to have a special condition, an interrupt
is generated when the character is loaded into the top four bytes of the FIFO. Therefore,
the Special Condition ISR must be RR1 before reading the data to determine which byte
has the special condition.
A new register, WR7’, has been added to the ESCC to enable the programming of six new
features. The format of this register is represented in
R/W
W
7
0
0
Value
W
6
0
Reserved, must be 0
Extended Read Enable
Transmit FIFO Int Level
DTR/REQ Timing Mode
Receive FIFO Int Level
Auto RTS Deactivation
Auto EOM Reset
Auto Transmit Flag
Description
W
5
0
/W
4
0
W
3
0
Table
4.
Z80230/Z85230 Enhancements
W
2
0
Product Specification
Z85230/Z80230
W
1
0
W
0
0
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