z85230 ZiLOG Semiconductor, z85230 Datasheet - Page 36

• Manufacturer Part Number: z85230
• Description: Enhanced Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

PS005303-0907
FIFO Write Operation
SDLC Status FIFO Anti-Lock Feature
(because the status FIFO is empty). The read from RR1 allows an entry to be read from the
FIFO (if the FIFO is empty, the logic prevents a FIFO underflow condition).
When the end of an SDLC frame is received and the Status FIFO is enabled, the contents
of the status and byte-count registers load into the FIFO. The EOF signal increments the
FIFO. If the FIFO overflows, the RR7 bit 7 (FIFO overflow) is set, indicating the over-
flow. This bit and the FIFO control logic is reset by disabling and re-enabling the FIFO
control bit (WR15 bit 2). For details about FIFO control timing during an SDLC frame,
see
When the Frame Status FIFO is enabled and the ESCC is programmed for Special Receive
Condition Only (WR1 bit 4 = bit 3=1), the data FIFO is not locked when a character with
EOF status is read.When EOF status is at the top of the FIFO, an interrupt with a vector
for receive data is generated. The command
end of the ISR regardless of whether an Interrupt Acknowledge cycle was executed (hard-
ware or software).
This action allows the DMA to complete the transfer of the received frame to memory,
then interrupt the CPU that a frame was completed, without locking the FIFO. Because in
the RECEIVE INTERRUPT ON SPECIAL CONDITION ONLY mode the interrupt vec-
tor for receive data is not used, it indicates that the last byte of a frame has been read from
the receive FIFO. Reading the frame status (CRC, byte count and other status stored in the
status FIFO) determines that EOF is not required.
When a character with a special receive condition other than EOF is received (receiver
overrun or parity), a special receive condition interrupt is generated after the character is
read from the FIFO and the receive FIFO is locked until the
issued.
Figure
Do not load
counter on
first flag.
reset byte
counter here
0
F
16.
1
A
Internal byte strobe
increments counter
Figure 16. SDLC Byte Counting Detail
2
D D
3
4
D
5
D C
6
Reset byte
counter, then
load counter
into FIFO and
increment PTR.
C
7
F
Reset Highest IUS
0
F
A
1
Error Reset
Internal byte strobe
increments counter
Z80230/Z85230 Enhancements
2
D D
Product Specification
3
must be issued at the
4
D
Z85230/Z80230
D C C
5
command is
6
Reset byte
counter, then
load counter
into FIFO and
increment PTR
7
0
F
31