mc33385vw/r2 Freescale Semiconductor, Inc, mc33385vw/r2 Datasheet - Page 14

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mc33385vw/r2

Manufacturer Part Number
mc33385vw/r2
Description
Quad Low-side Driver
Manufacturer
Freescale Semiconductor, Inc
Datasheet
CMOS input stages. Each output power transistor is
protected against short to V
overvoltage.
output stage : overcurrent, short to GND, open-load and
overtemperature.
read out via the serial interface (SPI).
OUTPUT STAGE CONTROL
an individual control line (NON-Input). The logic level of the
control line is CMOS compatible. The output transistors are
switched off when the inputs are not connected.
POWER TRANSISTORS
This causes a voltage limitation at the power transistors when
inductive loads are switched off. The drain voltage ramp
occurring when output is switched on or off, is within defined
limits. Output transistors can be connected in parallel to
increase current capability. In this case, the associated inputs
should be connected together.
SHORT-CIRCUIT AND OVERTEMPERATURE
PROTECTION
for a time longer than t
above T
switched off. It remains switched off until the control signal on
the NON-Input is switched off and on again.
DIAGNOSTICS
above the short current limit) or an overtemperature.
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33385
FUNCTIONAL DESCRIPTION
INTRODUCTION
The device is a Quad Low-side Driver driven by four
A diagnostic logic recognizes four failure types at the
The failures are individually stored in a byte which can be
Each of the four output stages is switched ON and OFF by
Each of the four output stages has its own zener clamp.
If the output current increases above the short current limit
The following failures at the output stage are recognized :
Short -Circuit to V
Short -Circuit to GND.................... = SCG
Open Load...................................... = OL (Lowest priority)
The SCB failure is recognized by an overcurrent (current
OFF
then the power transistor is immediately
BAT
SCB
or overtemp = SCB (Highest priority)
or if the temperature increases
BAT
by a zener clamp against
FUNCTIONAL DESCRIPTION
INTRODUCTION
IOL-reference, after a filter time an OL failure will be
recognized. This measurement is active while the power
stage is switched on.
lower than the OL reference limit, while the output stage is
switched off. All four outputs have an independent
overtemperature detection and shutdown. All failures are
stored in individual registers.
interface. There is no failure detected if the power stage
control time is shorter than the filter time.
DIAGNOSTIC INTERFACE
failure register runs via the SPI link. If there is a failure stored
in the failure register, the first bit of the shift register is set to
a high level. With the High/Low change on the NCS pin, the
first bit of the diagnostic shift register will be transmitted to the
SDO output. The SDO output is the serial output from the
diagnostic shift register and it is put into a tri-state when the
NCS pin is high. The CLK pin clocks the diagnostic shift
register. New SDO data will appear on every rising edge of
this pin and new SDI data will be latched on every CLK’s
falling edge into the shift register. With the first positive pulse
of the CLK, the failure register will be cleared. There is no bus
collision at a small spike at the NCS. The CLK is always LOW
while the NCS-signal is changing.
RESET
than V
failure-registers are reset.
circuits are reset :
UNDERVOLTAGE PROTECTION
if there is a voltage ramp at the OUT pin.
If the current through the output stage is lower than the
The SCG failure will recognize when the drain voltage is
They can be read by the microprocessor via the serial
The communication between the microprocessor and the
There are two different reset functions realized :
Under voltage reset : as long as the V
Reset pin : as long as the NRES-pin is low, following
• Power stages
• Failure register
At low V
CCRES
CC
, the power stages are switched off and the
voltage, the device remains switched off even
Analog Integrated Circuit Device Data
Freescale Semiconductor
CC
voltage is lower

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