adm6996f Infineon Technologies Corporation, adm6996f Datasheet - Page 41
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adm6996f
Manufacturer Part Number
adm6996f
Description
6 Port 10/100 Mb/s Single Chip Ethernet Switch Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.ADM6996F.pdf
(69 pages)
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ADM6996F
Infineon-ADMtek Co Ltd
4.3.13 Miscellaneous Configuration register, offset: 0x12h
4.3.14 VLAN mapping table registers, offset: 0x22h ~ 0x13h
4.3.15 Reserved Register, offset: 0x27h ~ 0x23h
Bits
15
14
13:12 R/W Power Saving Select
11
10:9
8
7
6
5
4
3
2
1
0
Bits
15:9
8:0
Bits
15:0
CPU. Because the WAN port need to be isolated from the LAN ports due to frames are
different and need to be translated by CPU. CPU will act as the bridge to transmit,
receive and translate frames between WAN and LAN. This isolated PHY can help to
reduce the BOM costs and improve the Gateway router’s performance.
Note:
16 VLAN Group: See Register 0x2ch bit 11=0
Bit0: Port0
Bit6: Port3
Select the VLAN group ports is to set the corresponding bits to 1.
Type Description
Type Description
Type Description
R/W Drop packet when excessive collision happen enable. 1: enable, 0:
R/W Reserved
R/W Reserved
R/W Reserved
R/W Port5 MAC Lock. 1: Lock first MAC source address, 0: disable.
R/W Port4 MAC Lock. 1: Lock first MAC source address, 0: disable.
R/W Port3 MAC Lock. 1: Lock first MAC source address, 0: disable.
R/W Reserved
R/W Port2 MAC Lock. 1: Lock first MAC source address, 0: disable.
R/W Reserved
R/W Port1 MAC Lock. 1: Lock first MAC source address, 0: disable.
R/W Reserved
R/W Port0 MAC Lock. 1: Lock first MAC source address, 0: disable.
R/W VLAN mapping table.
R/W Reserved
RO Reserved
disable.
Bit2: Port1
Bit7: Port4
Bit4: Port2
Bit8: Port5.
Register Description
Initial value
Initial value
Initial value
0x1ffh
0x7fh
0x0h
0x0h
0x3h
0x0h
0x3h
0x0h
0x0h
0x0h
0x0h
0x0h
0x0h
0x0h
0x0h
0x0h
0x0h
4-4