peb20550 Infineon Technologies Corporation, peb20550 Datasheet - Page 36

• Manufacturer Part Number: peb20550
• Description: Extended Pcm Interface Controller
• Manufacturer: Infineon Technologies Corporation

PEB 2055
PEF 2055
Operational Description
The offset can then be programmed such that PFS marks any bit number of the external
frame.
Furthermore it is possible to select either the rising or falling PDC-clock edge for
transmitting and sampling the PCM-data.
Usually, the repetition rate of the applied framing pulse PFS is identical to the frame
period (125 s). If this is the case, the loss of synchronism indication function can
be used to supervise the clock and framing signals for missing or additional clock cycles.
The EPIC checks the PFS-period internally against the duration expected from the
programmed data rate. If, for example, double clock operation with 32 time slots per
frame is programmed, the EPIC expects 512 clock periods within one PFS period. The
synchronous state is reached after the EPIC has detected two consecutive correct
frames. The synchronous state is lost if one bad clock cycle is found. The
synchronization status (gained or lost) can be read from an internal register and each
status change generates an interrupt.
3.4.2
Configurable Interface
The serial configurable interface (CFI) can be operated either in duplex modes or in a bi-
directional mode.
In duplex modes the EPIC-1 provides up to four ports (EPIC-S: up to two ports)
consisting each of a data output (DD) and a data input (DU) line. The output pins are
called “Data Downstream” pins and the input pins are called “Data Upstream” pins.
These modes are especially suited to realize a standard serial PCM interface (PCM
highway) or to implement an IOM (ISDN-Oriented Modular) interface. The IOM interface
generated by the EPIC offers all the functionality like C/I- and monitor channel handling
required for operating all kinds of IOM compatible layer-1 and codec devices.
In bi-directional mode the EPIC-1 provides eight bi-directional ports (SIP), the EPIC-S
four bi-directional ports, respectively. Each time slot at any of these ports can individually
be programmed as input or output. This mode is mainly intended to realize an SLD
interface (Serial Line Data). In case of an SLD interface the frame consists of eight time
slots where the first four time slots serve as outputs (downstream direction) and the last
four serve as inputs (upstream direction). The SLD interface generated by the EPIC
offers signaling and feature control channel handling.
Data is transmitted and received at normal TTL/CMOS-levels at the CFI. Tristate or
open drain output drivers can be selected. In case of open drain drivers, external
pull-up resistors are required. Unassigned output time slots may be switched to high
impedance or be programmed to transmit a defined idle value. The selection between
the states “high impedance” or “idle value” can be performed on a per time slot basis.
The CFI-standby function switches all CFI-output lines to high impedance with a single
command. Internally the device still works normally, only the output drivers are switched
off.
Semiconductor Group
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