tda19977a NXP Semiconductors, tda19977a Datasheet - Page 15

• Manufacturer Part Number: tda19977a
• Description: Triple Input Hdmi 1.3a Compliant Receiver Interface With Equalizer Up To 1080p For Hdtv, And Uxga For Pc Formats
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA19977A_TDA19977B_1
Product data sheet
8.19 4:2:2 formatter
8.20 Video port selection
8.21 Output buffers
8.22 VHREF timing generator
8.23 I
The 4:2:2 formatter contains the YCbCr 4:2:2 semi-planar and the YCbCr 4:2:2
ITU-R BT.656 formatting functions. The selection of these functions is made using the
I
The Start Active Video (SAV) and End Active Video (EAV) timing reference codes can be
included in the data stream based on the HREF, VREF and FREF positions from the
VHREF timing generator.
Specific codes programmed using the I
blanking period to mask gain and clamp calibration.
Each channel can be allocated to a specified video port using the I
“Output video port formats” on page
video processing ICs. For example:
Each video port can be set to high-impedance using the I
The levels of the output buffers are LV-TTL compatible. Switching the outputs between
active and high-impedance is set using the I
The outputs HREF, VREF and FREF can be set to high-impedance (Z) or forced LOW (L),
independently of the timing reference codes.
The VHREF timing generator outputs all of the timing signals used by the device:
The I
The slave address of the device is selected by pin A0.
2
2
C-bus.
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C-bus serial interface
In YCbCr 4:2:2 mode: the data frequency for the Y signal is equal to the pixel clock
frequency. While the data frequency for the Cb and Cr signals is equal to half the pixel
clock frequency
In semi-planar mode: the output clock should be the same as the pixel clock
In ITU-R BT.656 mode: the data frequency should be the same as the formatter clock
frequency (e.g. pixel clock
R, G or B in RGB 4:4:4 mode on VP[29:20]
Y, Cb or Cr in YUV 4:4:4 mode on VP[19:10]
Y or Cb-Cr in 4:2:2 semi-planar mode on VP[9:0]
Cb-Y-Cr-Y in 4:2:2 ITU-R BT.656 mode on VP[9:0]
VREF, HREF and FREF signals for SAV, EAV and active video area definition
VS and HS to change width and position compared with the HDMI inputs
2
C-bus serial interface enables the internal registers of the device to be programmed.
Rev. 01 — 7 August 2008
Triple input HDMI receiver interface with digital processing
2)
22) to optimize board layout at the interface with
TDA19977A; TDA19977B
2
C-bus can replace the data stream during the
2
C-bus.
2
C-bus.
2
C-bus (see
© NXP B.V. 2008. All rights reserved.
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