adm8513 Infineon Technologies Corporation, adm8513 Datasheet - Page 16

• Manufacturer Part Number: adm8513
• Description: Usb-to-10/100 Mbps Ethernet Lan Controller
• Manufacturer: Infineon Technologies Corporation

3
3.1
USB is a likely solution any time you want to use a computer to communication with devices outside the computer.
The interface is suitable for one-of-kind and small-scale designs as well as mass-produced, standard peripheral.
The benefits to USB are easy to use, fast and reliable data transfers, flexibility, low cost and power conservation.
3.1.1
SIE (Serial Interface Engine) is to control USB communications and check USB protocol, then transfer protocol to
EP decoder. The SIE and USB transceivers, which provide the hardware interface to the USB cable, together
comprise the USB engine.
3.1.2
The detail description is in “USB Command”.
3.2
FIFO Controller in receive path is in charge of:
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3.3
RX FIFO is a one-port 64-byte FIFO and TX FIFO is a two-port 2K-byte FIFO.
3.4
The Ethernet PHY is compliant to IEEE 802.3u 100BASE-TX and IEEE802.3 10BASE-T. It provides the whole
physical layer functions for both 10M and 100M Ethernet speed.
4
4.1
Endpoint 0 is in charge of response to standard USB commands and vendor specific commands. Internal register
settings are also via this endpoint. The response to each command is described in section 6.
Data Sheet
Stores received Ethernet packets to SRAM and multiple packets can be stored to SRAM. If more than
maximum packet counts are received or total packet size is more than the size of SRAM, the subsequent
coming Ethernet packet will be discarded.
FIFO controller will load data from SRAM to internal RX FIFO then inform EP Decoder that 64-byte data or a
packet is ready in RX FIFO. Before FIFO controller informs about this, any USB access to bulk IN endpoint will
return NAK. This is to maintain the data transfer on the USB bus via bulk IN transfer which is continuous, thus
a 64-byte internal RX FIFO is needed.
If an Ethernet packet is being received and loading into SRAM while FIFO Controller is moving data from
SRAM to internal RX FIFO, writing the Ethernet packet to SRAM will get the higher priority.
Function Description
USB Interface
SIE
USB Command & EP Decoder
FIFO Controller
TX FIFO and RX FIFO
10/100M Ethernet PHY
USB Device Endpoint Operation
Endpoint 0
16
Function Description
Rev. 1.21, 2005-12-05
Data Sheet
ADM8513