at89c51cc02ua-tdsum ATMEL Corporation, at89c51cc02ua-tdsum Datasheet - Page 94

• Manufacturer Part Number: at89c51cc02ua-tdsum
• Description: At89c51cc02, T89c51cc02 Enhanced 8-bit Microcontroller With Can Controller And Flash
• Manufacturer: ATMEL Corporation

Registers
94
AT/T89C51CC02
Table 56. CANGCON Register
CANGCON (S:ABh)
CAN General Control Register
Reset Value = 0000 0000b
ABRQ
Bit Number
7
7
6
5
4
3
2
1
0
OVRQ
6
Bit Mnemonic
AUTOBAUD
SYNCTTC
ENA/STB
OVRQ
ABRQ
GRES
TEST
TTC
TTC
5
Description
Abort Request
Not an auto-resetable bit. A reset of the ENCH bit (message object
control & DLC register) is done for each message object. The
pending transmission communications are immediately aborted but
the on-going communication will be terminated normally, setting
the appropriate status flags, TxOk or RxOk.
Overload Frame Request (Initiator).
Auto-resetable bit.
Set to send an overload frame after the next received message.
Cleared by the hardware at the beginning of transmission of the
overload frame.
Network in Timer Trigger Communication
set to select node in TTC.
clear to disable TTC features.
Synchronization of TTC
When this bit is set the TTC timer is caught on the last bit of the
End Of Frame.
When this bit is clear the TTC timer is caught on the Start Of
Frame.
This bit is only used in the TTC mode.
AUTOBAUD
set to active listening mode.
Clear to disable listening mode
Test mode. The test mode is intended for factory testing and not for
customer use.
Enable/Standby CAN Controller
When this bit is set, it enables the CAN controller and its input
clock.
When this bit is clear, the on-going communication is terminated
normally and the CAN controller state of the machine is frozen (the
ENCH bit of each message object does not change).
In the standby mode, the transmitter constantly provides a
recessive level; the receiver is not activated and the input clock is
stopped in the CAN controller. During the disable mode, the
registers and the mailbox remain accessible.
Note that two clock periods are needed to start the CAN controller
state of the machine.
General Reset (Software Reset).
Auto-resetable bit. This reset command is ‘ORed’ with the
hardware reset in order to reset the controller. After a reset, the
controller is disabled.
SYNCTTC
4
AUTOBAUD
3
TEST
2
ENA
1
4126L–CAN–01/08
GRES
0