sab-c161s-l25m Infineon Technologies Corporation, sab-c161s-l25m Datasheet - Page 66

• Manufacturer Part Number: sab-c161s-l25m
• Description: 16-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

Table 18
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1) RW-delay and
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet
Therefore address changes before the end of RD have no impact on read cycles.
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
t
1)
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
68
55
57
t
A
+
t
C
SR –
CC -6 +
CC 6 +
+
t
F
Min.
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
F
62
t
F
Max.
0 +
–
–
t
F
1 / 2TCL = 1 to 25 MHz
Min.
–
-6 +
TCL - 14
+
Variable CPU Clock
t
F
t
F
Timing Characteristics
Max.
TCL - 20
+ 2
–
–
t
A
V1.0, 2003-11
+
t
F
1)
C161S
Unit
ns
ns
ns