sab9077h NXP Semiconductors, sab9077h Datasheet - Page 9

• Manufacturer Part Number: sab9077h
• Description: Picture-in-picture Pip Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Pixel rate
The internal chrominance format used is 4 : 1 : 1. It is
expected that the bandwidth of the input signals is limited
to 4.5 MHz for the Y input and 1.125 MHz for the U/V
inputs.
The Y input is sampled with a 1728
clock and is filtered and down sampled to the internal
864
The U and V inputs are multiplexed and sampled with a
432
216
Acquisition area
Synchronization is done via the acquisition H
V
system constant the starting point of the acquisition can be
controlled.
The acquisition area is 672 pixels/line and 228 lines/field
for NTSC and 276 lines/field for PAL. Both main and
sub-channel are equivalent in handling the data.
Table 2 PIP sizes
1996 Aug 07
Pixels
NTSC-lines
PAL-lines
Sync
REDUCTION
Picture-In-Picture (PIP) controller
pins. With the acquisition fine positioning added to a
H
H
H
sync
sync
sync
( 13.5 MHz) pixel rate.
clock and down sampled to the internal
( 3.375 MHz) pixel rate.
672
H/1
336
H/2
H
sync
( 27.0 MHz)
Sync
224
H/3
and
9
168
H/4
Display mode
The internal display pixel rate is 864
13.5 MHz. This pixel rate is upsampled by interpolation to
1728
Display area
The display background is an area of 696 pixels for both
PAL and NTSC, 238 lines for NTSC and 286 lines for PAL.
This can be put on/off by the BGON bit independent of the
PIPON bits. This area can be moved by the display
background fine positioning (BGHFP and BGVFP).
Its colour is determined by the BGCOL and BGBRT bits.
Within this area PIPs are defined dependent on the
PIP mode. The PIP sizes are determined by the display
reduction factors as is shown in Table 2. Whether a PAL or
NTSC fixed number is used is depends on the DPAL bit.
The display fine positioning determines the location of the
PIPs with respect to the background. sub and
main-channel both have their independent PIP size and
location control, which is shown in Fig.3.
DPH
228
276
V/1
sync
before the DAC stage.
138
114
V/2
Preliminary specification
V/3
76
92
SAB9077H
DPH
sync
which is
V/4
57
69