tja1080 NXP Semiconductors, tja1080 Datasheet - Page 24

• Manufacturer Part Number: tja1080
• Description: Flexray Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TJA1080_2
Product data sheet
7.7.10 UV
7.7.11 UV
7.7.12 UV
7.7.13 Error flag
7.7.9 Bus error flag
7.8 TRXD collision
7.9 Status register
The bus error flag is set if pin TXEN is LOW and pin BGE is HIGH and the data received
from the bus lines (pins BP and BM) is different to that received on pin TXD. Additionally in
star configuration the bus error flag is also set if the data received on the bus lines is
different to that received on pins TRXD0 and TRXD1. The TJA1080 also expects that a
data frame begins with a bit value other than the last bit of the previous data frame.
This is the case for a valid data frame which begins with the DATA_0 period of the
Transmission Start Sequence (TSS) and ends with the DATA_1 bit of the Frame End
Sequence (FES). Any violation of this frame format will be detected by the TJA1080.
Consequently, when transmitting a wake-up pattern, a bus error will be signalled. This
error indication should be ignored and the status register should be cleared by reading the
vector.
No action will be taken if the bus error flag is set.
The UV
is reset if the voltage is higher than V
Section
The UV
t
than t
The UV
t
flag is set; see
The error flag is set if one of the status bits S4 to S12 is set. The error flag is reset if none
of the S4 to S12 status bits are set; see
A TRXD collision is detected when both TRXD lines are LOW in star configuration.
The status register can be read out on pin ERRN by using pin EN as clock; the status bits
are given in
The status register is accessible if:
Pin ERRN is LOW if the corresponding status bit is set.
det(uv)(VCC)
det(uv)(VIO)
•
•
VBAT
VCC
VIO
UV
UV
rec(uv)(VCC)
VIO
VCC
flag
VBAT
VCC
VIO
flag
7.6.1.
flag
. The flag is reset if the voltage on pin V
. The flag is reset if the voltage on pin V
flag is not set and the voltage on pin V
flag is set if the voltage on pin V
flag is not set and the voltage on pin V
flag is set if the voltage on pin V
Table
flag is set if the voltage on pin V
Section
or the wake flag is set; see
11. The timing diagram is illustrated in
7.6.3.
Rev. 02 — 12 July 2007
uvd(VBAT)
Table
IO
Section
CC
BAT
is lower than V
or by setting the wake flag; see
11.
is lower than V
is lower than V
IO
IO
IO
CC
is between 4.75 V and 5.25 V
7.6.2.
is higher than V
is between 2.2 V and 4.75 V
is higher than V
Figure
uvd(VIO)
uvd(VCC)
uvd(VBAT)
9.
for longer than
uvd(VIO)
FlexRay transceiver
uvd(VCC)
for longer than
© NXP B.V. 2007. All rights reserved.
TJA1080
. The UV
or the wake
for longer
VBAT
24 of 48
flag