adm1069ast-reel Analog Devices, Inc., adm1069ast-reel Datasheet - Page 28

• Manufacturer Part Number: adm1069ast-reel
• Description: Super Sequencer With Margining Control
• Manufacturer: Analog Devices, Inc.

ADM1069
SERIAL BUS INTERFACE
The ADM1069 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device,
under the control of a master device. It takes approximately
1 ms after power-up for the ADM1069 to download from its
EEPROM. Therefore, access to the ADM1069 is restricted until
the download is completed.
Identifying the ADM1069 on the SMBus
The ADM1069 has a 7-bit serial bus slave address (see Table 11).
The device is powered up with a default serial bus address. The
5 MSBs of the address are set to 10011; the 2 LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1069s to one SMBus.
Table 11. Serial Bus Slave Address
A0 Pin
Low
Low
High
High
1
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
Name
MANID
REVID
MARK1
MARK2
General SMBus Timing
Figure 35, Figure 36, and Figure 37 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
1.
X = Read/Write bit. The address is shown only as the first 7 MSBs.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data-line SDA, while the serial clock line SCL remains
high. This indicates that a data stream follows.
A1 Pin
Low
High
Low
High
Address
0xF4
0xF5
0xF6
0xF7
0x41
0x02
0x00
0x00
Hex Address
0x98
0x9A
0x9C
0x9E
Value
Function
Manufacturer ID for Analog
Devices
Silicon revision
Software brand
Software brand
7-Bit Address
1001100X
1001101X
1001110X
1001111X
1
1
1
1
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2.
3.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits, consisting
of a 7-bit slave address (MSB first) plus an R/ W bit. This
bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and by holding it low during the high
period of this clock pulse.
All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the
R/ W bit is a 0, the master writes to the slave device. If the
R/ W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-
high transition when the clock is high could be interpreted
as a stop signal. If the operation is a write operation, the
first data byte after the slave address is a command byte.
This tells the slave device what to expect next. It could be
an instruction telling the slave device to expect a block
write, or it could simply be a register address that tells the
slave where subsequent data is to be written. Because data
can flow in only one direction, as defined by the R/ W bit,
sending a command to a slave device during a read
operation is not possible. Before a read operation, it could
be necessary to perform a write operation to tell the slave
what sort of read operation to expect and/or the address
from which data is to be read.
When all data bytes have been read or written, stop condi-
tions are established. In write mode, the master pulls the
data line high during the 10
condition. In read mode, the master device releases the
SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is known
as no acknowledge. The master then takes the data line low
during the low period before the 10
high during the 10
th
clock pulse to assert a stop condition.
th
clock pulse to assert a stop
th
clock pulse, and then