el9115 Intersil Corporation, el9115 Datasheet - Page 8

• Manufacturer Part Number: el9115
• Description: Triple Analog Video Delay Line
• Manufacturer: Intersil Corporation

Test Pins
Three test pins are provided (Test R, Test G, Test B) during
normal operation the test pins output pulses of current for a
duration of the overlap between the inputs as shown in
Figure 14:
Test_R pulse = Red out (A) wrt Green out (B)
Test_G pulse = Green out
Test_B pulse = Blue out
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B the current
pulse is +50µA, and the output voltage goes up. When B
precedes A the pulse is –50µA.
For the logic to work correctly A and B must have a period of
overlap whilst they are high. I.e. a delay longer than the
pulse width cannot be measured.
The signals A and B are derived from the video input by
comparing the video signal with a slicing level which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signals encoded on
top of the video or from a dedicated set-up signal. The
outputs can be used to set the correct delays for the signals
received.
The DAC level is set through the serial input by bits 1-4
directed to the test register (00).
Test Mode
Bit zero of the test register is set to 0 for normal operation. If
it is set to 1 then the device is in test mode. In Test Mode the
DAC voltage is directed to the Green channel output whilst
for the Red and Blue channels, the test outputs are now
pulses of current which are generated by looking at the delay
between the input and output of the channel. They thus
enable the delay to be measured.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
For information regarding Intersil Corporation and its products, see www.intersil.com
wrt Red out
wrt Blue out
8
EL9115
NOTES:
Test Register word = 000wxyzt
If t = 1 test mode else normal
wxyz fed to DAC. z is LSB
wxyz
1000
1001
1010
1011
1100
1101
0000
0001
0010
0011
0100
0101
0110
1110
1111
0111
FIGURE 14. DELAY DETECTOR
TABLE 2.
DAC/mV
-400
-350
-300
-250
-200
-150
-100
100
150
200
250
300
350
-50
50
0
October 12, 2006
FN7441.3