ptn3360d NXP Semiconductors, ptn3360d Datasheet

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ptn3360d

Manufacturer Part Number
ptn3360d
Description
Enhanced Performance Hdmi/dvi Level Shifter With Active Ddc Buffer, Supporting Deep Color Mode
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
The PTN3360D is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals, up to 2.5 Gbit/s per lane to support 36-bit
deep color mode. Each of these lanes provides a level-shifting differential buffer to
translate from low-swing AC-coupled differential signaling on the source side, to
TMDS-type DC-coupled differential current-mode signaling terminated into 50 Ω to 3.3 V
on the sink side. Additionally, the PTN3360D provides a single-ended active buffer for
voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side
and provides a channel with active buffering and level shifting of the DDC channel
(consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The
DDC channel is implemented using active I
isolation, redriving and level shifting as well as disablement (isolation between source and
sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3360D typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI
or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0
or HDMI v1.3a specification. By using PTN3360D, chip set vendors are able to implement
such reconfigurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure
The PTN3360D main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of DisplayPort
Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The
I
capacitive isolation. The PTN3360D also supports power-saving modes in order to
minimize current consumption when no display is active or connected.
The PTN3360D is a fully featured HDMI as well as DVI level shifter. The PTN3360D
supersedes PTN3360B, and provides a better high speed performance with a
programmable equalizer.
PTN3360D is powered from a single 3.3 V power supply consuming a small amount of
power (230 mW typ.) and is offered in a 48-terminal HVQFN48 package. PTN3360D has
two pinning options. PTN3360DBS has its pin 6 as REXT to provide a higher accuracy
current reference, and PTN3360DBS/S900 pin 6 is not connected providing more
flexibility. See
2
C-bus channel actively buffers as well as level-translates the DDC signals for optimal
PTN3360D
Enhanced performance HDMI/DVI level shifter with active DDC
buffer, supporting deep color mode
Rev. 01 — 16 June 2010
1.
Section 7.2
for details.
2
C-bus buffer technology providing capacitive
Product data sheet

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ptn3360d Summary of contents

Page 1

... PTN3360B, and provides a better high speed performance with a programmable equalizer. PTN3360D is powered from a single 3.3 V power supply consuming a small amount of power (230 mW typ.) and is offered in a 48-terminal HVQFN48 package. PTN3360D has two pinning options. PTN3360DBS has its pin 6 as REXT to provide a higher accuracy current reference, and PTN3360DBS/S900 pin 6 is not connected providing more flexibility ...

Page 2

... HPD_SOURCE quinary input EQ5 DDC_EN 3 3.3 V) 3.3 V SCL_SOURCE 3.3 V SDA_SOURCE All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D PTN3360D OUT_D4+ OUT_D4− OUT_D3+ OUT_D3− OUT_D2+ OUT_D2− OUT_D1+ OUT_D1− HPD_SINK 5 V SCL_SINK ...

Page 3

... Power-saving modes (using output enable) Back-current-safe design on all sink-side main link, DDC and HPD terminals Transparent operation: no re-timing or software configuration required 48-terminal HVQFN48 package with two pinning options. PTN3360DBS has its pin 6 as REXT, and PTN3360DBS/S900 pin 6 is not connected. 3. Applications ...

Page 4

... Ordering options Topside mark Configuration of Pin 6 PTN3360DBS pin 6 is the REXT signal; see PTN3360DSS pin 6 is not connected All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 ...

Page 5

... NXP Semiconductors 5. Functional diagram DDC_EN ( 3.3 V) Fig 2. Functional diagram of PTN3360D PTN3360D_1 Product data sheet HDMI/DVI level shifter supporting deep color mode OE_N input bias enable 50 Ω 50 Ω IN_D4+ EQ IN_D4− input bias enable 50 Ω 50 Ω IN_D3+ EQ IN_D3− input bias enable 50 Ω ...

Page 6

... PCB in the thermal pad region. Fig 3. Pin configuration for HVQFN48 (PTN3360DBS) PTN3360D_1 Product data sheet HDMI/DVI level shifter supporting deep color mode ...

Page 7

... PCB in the thermal pad region. Fig 4. Pin configuration for HVQFN48 (PTN3360DBS/S900) 6.2 Pin description Table 3. Symbol OE_N, IN_Dx and OUT_Dx signals ...

Page 8

... TMDS differential output All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D Description Low-swing differential input from display source with PCI Express electrical signalling. IN_D4− makes a differential pair with IN_D4+. The input to this pin must be AC coupled externally ...

Page 9

... All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D Description HDMI compliant TMDS output. OUT_D2− makes a differential pair with OUT_D2+. OUT_D2− phase with IN_D2−. HDMI compliant TMDS output. OUT_D1+ makes a differential pair with OUT_D1− ...

Page 10

... The PTN3360D also provides voltage translation for the Hot Plug Detect (HPD) signal from the sink side 3 the source side. The PTN3360D does not re-time any data. It contains no state machines. No inputs or outputs of the device are latched or clocked. Because the PTN3360D acts as a transparent level shifter, no reset is required ...

Page 11

... The following sections and truth table describe their detailed operation. 7.1.1 Hot plug detect The HPD channel of PTN3360D functions as a level-shifting buffer to pass the HPD logic signal from the display sink device (via input HPD_SINK the display source device (via output HPD_SOURCE). ...

Page 12

... SCL_SOURCE high-impedance zero output current SDA_SINK zero output current connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D Mode [4] [5] HPD_SOURCE LOW Active; DDC disabled LOW Active; DDC enabled LOW Standby LOW Standby ...

Page 13

... DDC I/Os and the HPD_SINK input. This supports user scenarios where the display is connected and powered, but the PTN3360D is unpowered. In these cases, the PTN3360D will sink no more than a negligible amount of leakage current, and will block the display (sink) termination network from driving the power supply of the PTN3360D or that of the inactive DVI or HDMI source ...

Page 14

... NXP Semiconductors PTN3360D has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK) only. During positive bus transitions on the sink-side port, a current source is switched on to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus V threshold level of around 1 exceeded, and turns off as the 5 V DDC bus V threshold voltage of approximately 3 ...

Page 15

... RX(cm Conditions logic 1 and logic 0 state applied respectively to differential inputs IN_Dn; R connected ref(ext) (PTN3360DBS only); see Table 7 single-ended intra-pair inter-pair jitter contribution is nominally 3 All information provided in this document is subject to legal disclaimers. ...

Page 16

... HPD_SINK HPD_SOURCE HPD_SOURCE from HPD_SINK to HPD_SOURCE HPD_SOURCE rise/fall HPD_SINK input pull-down resistor or from Conditions OE_N pin minimum. IL All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D Min Typ Max [1] 2.0 5 ...

Page 17

... 4.5 V; CC2 slew rate = 1.25 V/μs All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D Min Typ Max Unit 0.7V - 3.6 V CC1 −0.5 - +0.3V V CC1 −0.5 0 μ μ ...

Page 18

... 5.25 7.1 5.25 0.5 0.5 5.5 5.5 4.95 6.9 4.95 0.3 REFERENCES JEDEC JEITA MO-220 - - - All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D SOT619 detail 0.05 0.1 0.1 0.05 EUROPEAN ISSUE DATE PROJECTION 01-08-08 02-10-18 © NXP B.V. 2010. All rights reserved. ...

Page 19

... Solder bath specifications, including temperature and impurities PTN3360D_1 Product data sheet HDMI/DVI level shifter supporting deep color mode All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D © NXP B.V. 2010. All rights reserved ...

Page 20

... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 6. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D Figure 6) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...

Page 21

... Hot Plug Detect Inter-IC bus Input/Output Negative-channel Metal-Oxide Semiconductor Transition Minimized Differential Signaling Video Electronic Standards Association All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...

Page 22

... PTN3360D_1 Product data sheet HDMI/DVI level shifter supporting deep color mode Data sheet status Change notice Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D Supersedes - © NXP B.V. 2010. All rights reserved ...

Page 23

... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D © NXP B.V. 2010. All rights reserved ...

Page 24

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 01 — 16 June 2010 PTN3360D © NXP B.V. 2010. All rights reserved ...

Page 25

... Enable and disable features . . . . . . . . . . . . . . 11 7.1.1 Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . 11 7.1.2 Output Enable function (OE_N 7.1.3 DDC channel enable function (DDC_EN 7.1.4 Enable/disable truth table . . . . . . . . . . . . . . . . 12 7.2 Analog current reference (PTN3360DBS only) 13 7.3 Equalizer 7.4 Backdrive current protection . . . . . . . . . . . . . . 13 7.5 Active DDC buffer with rise time accelerator . 13 8 Limiting values Recommended operating conditions ...

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