sta333bwqs13tr STMicroelectronics, sta333bwqs13tr Datasheet - Page 48

• Manufacturer Part Number: sta333bwqs13tr
• Description: 2.1-channel High-efficiency Digital Audio System With Qsound Qhd
• Manufacturer: STMicroelectronics

Register description
6.11
6.11.1
6.11.2
6.11.3
6.11.4
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Table 62.
Dynamics control registers (0x12 to 0x15)
Limiter 1 attack/release rate
Limiter 1 attack/release threshold
Limiter 2 attack/release rate
Limiter 2 attack/release threshold
The STA333BWQS includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode or to actively reduce the dynamic range for a better listening
environment such as a night-time listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in Configuration Register F, bit 0 address 0x05. Each
channel can be mapped to either limiter or not mapped, meaning that channel will clip when
0dBFS is exceeded. Each limiter looks at the present value of each channel that is mapped
to it, selects the maximum absolute value of all these channels, performs the limiting
algorithm on that value, and then if needed adjusts the gain of the mapped channels in
unison.
The limiter attack thresholds are determined by the LxAT registers. It is recommended in
anti-clipping mode to set this to 0dBFS, which corresponds to the maximum unclipped
output power of a DDX amplifier. Since gain can be added digitally within STA333BWQS it is
possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when
BTC[3:0]/TTC[3:0]
L1AT3
L2AT3
L1A3
L2A3
D7
D7
D7
D7
0
0
0
0
1101
1110
1111
Tone control boost/cut as a function of BTC and TTC bits
L1AT2
L2AT2
L1A2
L2A2
D6
D6
D6
D6
1
1
1
1
L1AT1
L2AT1
L1A1
L2A1
D5
D5
D5
D5
1
1
1
1
L1AT0
L2AT0
L1A0
L2A0
D4
D4
D4
D4
0
0
0
0
L1RT3
L2RT3
L1R3
L2R3
D3
D3
D3
D3
1
1
1
1
Boost/Cut
+12 dB
+12 dB
+12 dB
L1RT2
L2RT2
L1R2
L2R2
D2
D2
D2
D2
0
0
0
0
L1RT1
L2RT1
L1R1
L2R1
D1
D1
D1
D1
1
0
1
0
STA333BWQS
L1RT0
L2RT0
L1R0
L2R0
D0
D0
D0
D0
0
1
0
1