z86230 ZiLOG Semiconductor, z86230 Datasheet - Page 21

• Manufacturer Part Number: z86230
• Description: Advanced Violence Blocking And Ntsc Line 21 Xds
• Manufacturer: ZiLOG Semiconductor

4.1.5 Clock and Data Transitions
4.1.6 START Condition
PS000400-TVC0499
I
All
set, a 2- or multiple-byte
START
attempt to read any data bytes or the required data can be lost from the Z86230
output registers. The I
to acknowledge the received byte. This sequence is repeated until the
becomes true.
N
most recent byte read from the Z86230 should be acknowledged by the master with a Not
Acknowledge (NACK). The DAV bit of the Serial Status Register (
master clocking out the eighth bit of the first data byte read. The DAV bit is never cleared
by just reading the SSR (One Byte READ) alone. All data is output MSB first.
The master’s sequence for reading two data bytes (total of 3 bytes including SSB)
from the Z86230 is:
F
The
SDA
SCLK
A High-to-Low transition of
must precede any other command.
N
acknowledged by the master with a NACK (Not ACKnowledge).
2
IGURE
C B
OTE
I 2 C Three-Byte READ (Status, Data1, & Data2)
I 2 C One-Byte READ (Status Only)
I 2 C Two-Byte READ (Status & Data1)
OTE
READ
Start
Slave_Address_Read/Slave_ACK
SS_Byte/Master ACK
First_Byte/Master ACK
Second_Byte/Master_NACK
Stop
SCLK
US
:
: In all I
bus may only change during
START
START
START
In all I
High periods indicate a
5. I
O
condition. If the
PERATION
sequences output the
and
2
2
2
C B
C READ operations, the most recent byte read from the Z86230 must be
C READ operations (1-, 2- and 3-byte reads are illustrated in Figure 5), the
(READ=29h for the 1
SDA
(READ=29h for the 1
(READ=29h for the 1
SLAVE ADDR
SLAVE ADDR
US
SLAVE ADDR
Z86230—PRELIMINARY
READ (C
bus lines are normally pulled High with a resistor. Data on the
2
C master device should end the
DAV
READ
OMMAND
st
st
st
SDA
SERIAL STATUS
SERIAL STATUS
SERIAL STATUS
I
I
I
2
2
bit is not set, the I
2
START
C Address and 2Bh for the 2
C Address and 2Bh for the 2
C Address and 2Bh for the 2
SSR
sequence can be initiated, beginning with a
SCLK
with
)
first. If the Serial Status register
or
SCLK
NACK
Low time periods. Data changes during
STOP
READ DATA1
STOP
READ DATA1
S
High is a
ERIAL
condition as defined in Table 6.
2
nd
nd
nd
C master device should not
I
I
2
I
2
C Address)
2
C Address)
C Address)
C
NACK
OMMUNICATIONS
READ
START
STOP
READ DATA2
SSR
sequence by failing
condition which
) is cleared by the
NACK
DAV
DAV
I
NTERFACE
STOP
bit is
bit
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