lmf60 National Semiconductor Corporation, lmf60 Datasheet - Page 9

• Manufacturer Part Number: lmf60
• Description: High Performance 6th-order Switched Capacitor Butterworth Lowpass Filter
• Manufacturer: National Semiconductor Corporation

Crosstalk Test Circuits
Pin Description
Pin
FILTER OUT (3)
FILTER IN (8)
V
AGND (5)
V
INV1 (13)
V
INV2 (14)
NINV2 (1)
V
OS
O1
O2
a
(4)
(2)
(6) V
ADJ (7)
b
(10)
Description
The output of the lowpass filter will typi-
cally swing to within 1V of each supply
rail
The input to the lowpass filter To mini-
mize gain errors the source impedance
that drives this input should be less than
2k (See Section 1 4) For single supply
operation the input signal must be bi-
ased to mid-supply or AC coupled
This pin is used to adjust the DC offset
of the filter output if not used it must be
tied to the AGND potential (See Section
1 3)
The analog ground pin This pin sets the
DC bias level for the filter section and
the noninverting input of Op-Amp
and must be tied to the system ground
for split supply operation or to mid-sup-
ply for single supply operation (See Sec-
tion 1 2) When tied to mid-supply this
pin should be well bypassed
V
ing input of Op-Amp
ing input of this Op-Amp is internally
connected to the AGND pin
V
input and NINV2 is the non-inverting in-
put of Op-Amp
The positive and negative supply pins
The total power supply range is 4V to
14V Decoupling these pins with 0 1 mF
capacitors is highly recommended
O1
O2
is the output and INV1 is the invert-
is the output INV2 is the inverting
(Pin Numbers)
2
1 The non-invert-
From Either Op-Amp to Filter Output
From Filter to Op-Amps
1
9
Pin
CLK IN (9)
CLK R (11)
L Sh (12)
Description
A CMOS Schmitt-trigger input to be
used with an external CMOS logic level
clock
Schmitt-trigger oscillator (See Section
1 1)
A TTL logic level clock input when in
split supply operation (
L Sh tied to system ground This pin be-
comes a low impedance output when
L Sh is tied to V
tion with the CLK IN pin for self clocking
Schmitt-trigger oscillator (See Section
1 1)
Level shift pin selects the logic thresh-
old levels for the desired clock When
tied to V
STATE
Schmitt trigger and the internal clock
level shift stage thus enabling the CLK
IN Schmitt-trigger input and making the
CLK R pin a low impedance output
When the voltage level at this input ex-
ceeds 25% (V
ternal TRI-STATE buffer is disabled al-
lowing the CLK R pin to become the
clock input for the internal clock level
shift stage The CLK R threshold level is
now 2V above the voltage applied to the
L Sh pin Driving the CLK R pin with TTL
logic
through the use of split supplies and by
tying the L Sh pin to system ground
levels
Also
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