cp2120 Silicon Laboratories, cp2120 Datasheet - Page 15

• Manufacturer Part Number: cp2120
• Description: Single Chip Spi To I2c Transfer Integrated Clock; No External Clock Required On-chip Voltage Monitor
• Manufacturer: Silicon Laboratories

The SPI2I2C provides additional SMBus-related timers to enable I
Free Detect enables the device to poll the SMBus lines and determine when a transfer can begin. Setting the SCL
Low Time Out detect will cause an SMBus transaction to abort if the SCL line has been held low by a device for a
period of approximately 25 ms.
6.3. I
The CP2120 maintains an Internal Register, I2CSTAT, which describes the current status of the I
I2CSTAT register can be read at any time. The CP2120 updates I2CSTAT when an I
an I
It is not recommended that an SPI master poll the CP2120's I2CSTAT Internal Register to determine when an I
transaction has completed. The SPI master should instead watch for the INT pin to drop low, and then read the
I2CSTAT register to determine the I
Internal Register Address: 0x09
2
C transaction completes (successfully or unsuccessfully), and when a received SPI command contains errors.
2
C Status
Reserved
R/W
Bit 7
Reset Value:
Internal Register Definition 4. I2CTO2: Additional I
Reserved
Bit 1:
Bit 0:
Bit 6
R/W
0x00
I
0: Bus Free Detect Disabled
1: Bus Free Detect Enabled
0: SCL Low Time Out Detect disable
1: SCL Low Time Out Detect enable
I
2
2
C Bus Free Detect
C SCL Low Time Out Detect
Reserved
2
R/W
Bit 5
C transaction results.
Reserved
R/W
Bit 4
Rev. 0.3
Reserved
R/W
Bit3
2
C protocol compatibility. Setting the I
Reserved
R/W
Bit 2
2
C Time Outs
FREN
2
C transaction begins, when
R/W
Bit 1
2
CP2120
LWEN
C Interface. The
Bit 0
R/W
2
C Bus
2
15
C