tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 82

• Manufacturer Part Number: tda5235
• Description: Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
• Manufacturer: Infineon Technologies Corporation

2.5.2
The Receive FIFO is the storage of the received data frames and is only used in the POF
Mode. It is written during data reception. The host microcontroller is able to start reading
via SPI right after frame sync (interrupt) or in the most common case right after detection
of EOM (interrupt). The FIFO can store up to 256 received data bits. If the expected data
transmission contains more bits (note that in TSI 8-bit Extended Mode one bit is added
in front of the real payload to indicate which of the two TSI pattern has matched), reading
from FIFO must start a certain time after frame sync to prevent an overrun.
Architecture
The 256-bit receive FIFO is based on a bit-addressable 2-port memory architecture.
Figure 53
The write port is controlled by the Digital Receiver using the Write Address Pointer.
Writing data into the FIFO starts with the detection of a TSI. The Write Address Pointer
is incremented with each data clock signal generated by the Digital Receiver. The read
port is controlled by the SPI controller using the Read Address Pointer. Each bit read
from the SPI controller increments the Read Address Pointer. The Read and Write
Address Pointers jump from their maximum value (255
FIFO stops at EOM or after Sync loss.
Data Sheet
Receiver
Receiver
Digital-
Digital-
from FSM
from
from
FSINITFIFO
INITFIFO
Receive FIFO
InitFIFO
Data
Data Clock
FSync
EOM
FIFOLK
Receive FIFO
Write Address
ENABLE
(Up-Counter)
Controller
Pointer
FIFO-
RESET
FIFO-Overflow
# of Valid Bits
Bit-Address
Write-Port
byte 0
byte 1
byte 2
byte 3
byte 4
byte 5
byte 6
byte 7
byte 8
byte 9
byte 10
byte 11
byte 12
byte 13
byte 14
byte 15
82
1 of 16 Decoder
Memory-Array
16 to 1 MUX
SDO-Frame
Generator
256-bit
Out
In
byte 16
byte 17
byte 18
byte 19
byte 20
byte 21
byte 22
byte 23
byte 24
byte 25
byte 26
byte 27
byte 28
byte 29
byte 30
byte 31
Read-Port
Bit-Address
d
) to address zero. Writing to the
RESET
Read Address
(Up-Counter)
Pointer
ENABLE
Functional Description
V1.0, 2010-02-19
SCLK
fifolk
SDO
TDA5235
to
SPI-Bus
to FSM