lmp7312max National Semiconductor Corporation, lmp7312max Datasheet - Page 17

• Manufacturer Part Number: lmp7312max
• Description: Lmp7312 Precision Spi-programmable Afe With Differential/single-ended Input/output
• Manufacturer: National Semiconductor Corporation

In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations.
Daisy Chain
The LMP7312 supports daisy chaining of the serial data
stream between multiple chips. To use this feature serial data
is clocked into the first chip SDI pin, and the next chip SDI pin
is connected to the SDO pin of the first chip. Both chips may
share a chip select signal, or the second chip can be enabled
Shared 4-wire SPI with ADC
The LMP7312 is a good choice when interfacing to differential
analog to digital converters ADC141S626 and ADC161S626
of PowerWise® Family. Its SPI interface has been designed
to enable sharing CSB with the ADC. LMP7312 register ac-
cess happens only when CSB is asserted low while SCK is
high. However, the ADC starts conversion under any of the
following conditions: (1) CSB goes low while SCK is high, (2)
Gain_1
MSB
0
0
1
1
1
1
x
x
Gain_0
0
1
0
1
0
1
x
x
EN_CL
0
0
0
0
1
1
x
x
FIGURE 7. 4-wire SPI with ADC interface
Null_SW
FIGURE 6. Daisy chain
0
0
0
0
0
0
x
1
Hi_Z
LSB
17
0
0
0
0
0
0
1
0
separately. When the chip select pin goes low on both chips
and 5 bits have been clocked into the first chip the next 5 clock
cycle begins moving new configuration data into the second
chip. With a full 10 clock cycles both chips have valid data and
the chip select pin of both chips should be brought high to
prevent the data from overshooting.
CSB goes low while SCK is low, (3) CSB and SCK both going
low. Therefore, if a system uses timing condition #2 above,
LMP7312 and ADC1x1S626 can share CSB and SCK as
shown in
to LMP7312 triggers an ADC conversion, but then the result
can be ignored. At other times, the LMP7312 is not affected
by the CSB assertions used to initiate normal ADC conver-
sions.
Gain Value
0.096
0.192
0.384
0.768
(V/V)
1
2
–
1
Figure
7. The only side-effect would be that writing
High Impedance Output
Mode of Operation
Amplification Mode
Amplification Mode
Attenuation Mode
Attenuation Mode
Attenuation Mode
Attenuation Mode
Null Switch Mode
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