lm2512asnx National Semiconductor Corporation, lm2512asnx Datasheet - Page 13

• Manufacturer Part Number: lm2512asnx
• Description: Mobile Pixel Link Mpl-1 , 24-bit Rgb Display Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

Name
Command
Configuration
(Note 13)
Red RAM Address
Red RAM Data
Green RAM Address
Green RAM Data
Blue RAM Address
Blue RAM Data
Dither Configuration1
(Note 13)
Dither Configuration2
(Note 13)
Lane Scale
(Notes 13, 15)
Reserved
(Note 14)
Device Select
(Unlock/Lock)
Reserved
(Note 14)
LM2512A SPI Registers
Note 12: If a WRITE is done to a reserved bits, data should be all 0’s. If a READ is done to a reserved location, either 1’s or 0’s may be returned. Mask reserved
data bits.
Note 13: This register must be unlocked fist through bit 4 of register 0.
Note 14: DO NOT write to Reserved Registers.
Note 15: WRITE ONLY Register, read of this register is not supported.
Addre
0x0B-
0x17-
0x0A
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x15
0x16
0x7F
ss
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
na
na
W
Description
Bit 0 = LUT Enable
Bit 4 = Special Register Access
For access to Registers 0x01, 0x08, 0x09, 0x0A, the Special Register Access
bit must be unlocked. Must write all 8 bits.
Bit 4 = MPL Edge Rate
All other bits reserved, must be written as 0s.
Red Address
Red Data
Green Address
Green Data
Blue Address
Blue Data
Bit 0 - Dither Bypass
Bit 1 - DE INV
Bit 2 - VS INV
Bit 3 - Reserved
Bit 4 - Tempen0
Bit 5 - Tempen1
Bit 6 - Dith3 - Dither Amplitude
Bit 7 - Reserved
Dither Parameter
Reserved, Default value recommended.
Bit[2:0]
000’b = Reserved
010’b = 2 MD Lanes (Default)
100’b = 3 MD Lanes
all others= Reserved
Reserved
0xFF’h enables LM2512A SPI
All other values disables LM2512A SPI (0x00 to 0xFE)
Reserved
0’b = LUT Disabled, 1’b = LUT Enabled
0’b = SRA Locked, 1’b = SRA Unlocked
0’b = normal edge, 1’b = slow edge
1’b = Bypass Dither, 0’b = Dither ON
1’b = Active Low DE, 0’b = Active High DE
Does not alter DE signal, dither block input only.
1’b = Active Low VS signal, 0’b = Active High VS signal.
Does not alter VS signal, dither block input only.
1’b = Transposed Dither Pattern,
0’b = Even and odd frames use same dither pattern
1’b = Temporal Dithering is Enabled, 0’b = Disabled
1’b = set to 3 bits, 0’b = set to 4 bits
13
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Default
XX’h
XX’h
XX’h
00’h
00’h
00’h
00’h
00’h
61’h
67’h
02’h
00’h