p82b96td/s410 NXP Semiconductors, p82b96td/s410 Datasheet - Page 15
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p82b96td/s410
Manufacturer Part Number
p82b96td/s410
Description
Dual Bi-directional Bus Buffer
Manufacturer
NXP Semiconductors
Datasheet
1.P82B96TDS410.pdf
(28 pages)
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
P82B96TD/S410
Manufacturer:
NXP
Quantity:
28 000
NXP Semiconductors
P82B96_6
Product data sheet
Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times
Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times
V
CCM
MASTER
Effective delay of SCL at slave: 255 + 17V
C = F; V = volts.
Effective delay of SCL at master: 270 + RmCm + 0.7RbCb ns.
C = F; R = .
I
2
C-BUS
local master bus
10.1 Calculating system delays and bus clock frequency for a Fast mode
GND (0 V)
SCL
system
V
CCM
MASTER
I
2
C-BUS
Rm
Cm
master bus
capacitance
local master bus
GND (0 V)
V
CCB
Sx
SCL
P82B96
CCM
Rev. 06 — 31 January 2008
+ (2.5 + 4
Tx/Rx
Rm
buffered expansion bus
Cm
master bus
capacitance
V
CCB
Sx
10
Cb
buffered bus
wiring capacitance
Rb
9
P82B96
Tx/Rx
C
b
)V
CCB
buffered expansion bus
P82B96
+ 10V
Tx/Rx
CCS
Sx
ns.
Rb
Cb
buffered bus
wiring capacitance
Tx/Rx
Dual bidirectional bus buffer
002aab992
Rs
Cs
slave bus
capacitance
remote slave bus
SCL
© NXP B.V. 2008. All rights reserved.
I
P82B96
2
C-BUS
SLAVE
002aab991
V
CCS
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