sclt3-8bt8-tr STMicroelectronics, sclt3-8bt8-tr Datasheet - Page 9

• Manufacturer Part Number: sclt3-8bt8-tr
• Description: Protected Digital Input Termination With Serialized State Transfer
• Manufacturer: STMicroelectronics

SCLT3-8BT8
2.4
Figure 6.
Operation of the SCLT with the SPI bus
The SPI bus master controller manages the data transfer with the chip select signal /CS and
controls the data shift in the register with the clock SCK signal. This data transfer operation
is defined by the phase C
master protocol mode: C
Figure 7.
The transfer of the SCLT input state in the SPI register starts when the chip select signal
/CS falls and ends when this chip select signal rises back.
The transfer of data out of the SCLT slave MISO output starts immediately when the chip
select signal /CS goes low. The input MOSI is captured and presented to the shift register
on each rising edge of the clock SCK. The data are shifted in this register on each falling
edge of the serial clock SCK, the data bits are written on the output MISO with the most
significant bit first.
During all operations, V
DATA CAPTURE
DATA CAPTURE
MOSI
MOSI
MISO
MISO
SCK
SCK
CS
CS
Two-step digital filter placed after the analog section of the logic input
Serial data format frame with a master running in C
mode
CKF
CKF
IN
IN
MSB
MSB
MSB
MSB
S
S
OUT
OUT
CKF
CKF
M
M
D
D
D
CK
CK
CK
DD
IN
IN
1
1
1
1
PHA
PHA
is held stable within the specified operating range.
/Q
/Q
/Q
Q
Q
Q
14
14
14
14
= 0 and C
and the polarity C
Doc ID 15191 Rev 3
2
2
2
2
D
D
D
CK
CK
CK
13
13
13
13
3
3
POL
3
3
/Q
/Q
/Q
Q
Q
Q
= 0.
12
12
12
12
4
4
4
4
POL
D
D
D
CK
CK
CK
of the clock. The SCLT runs with an SPI
3
3
3
3
/Q
/Q
/Q
Q
Q
Q
13
13
13
13
2
2
2
2
14
14
14
14
S
S
S
S
R
R
R
R
1
1
1
1
Functional description
PHA
15
15
15
15
Q
Q
Q
= 0 and C
LSB
LSB
LSB
LSB
OUT
OUT
M
M
S
S
16
16
16
16
MSB
MSB
MSB
MSB
POL
S
S
M
M
= 0
9/33