qlx411riq Intersil Corporation, qlx411riq Datasheet
qlx411riq
Related parts for qlx411riq
qlx411riq Summary of contents
Page 1
Quad Lane Extender QLx411GRx The QLx411GRx is a settable quad receive-side equalizer with extended functionality for advanced protocols operating with line rates up to 11.3Gb/s such as InfiniBand (SDR, DDR and QDR) and 40G Ethernet (40GBase-CR4). The QLx411GRx compensates for ...
Page 2
... QLX411RIQT7 QLX411RIQ QLX411RIQSR QLX411RIQ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
Page 3
Pin Descriptions PIN NAME PIN NUMBER DT 1 Detection Threshold. Reference DC voltage threshold for input signal power detection. Data output OUT[k] is muted when the power of the equalized version of IN[k] falls below the threshold. Tie to ground ...
Page 4
Absolute Maximum Ratings Supply Voltage (V to GND -0.3V to 1.3V DD Voltage at All Input Pins . . . . . . . . . . . ...
Page 5
Electrical Specifications Typical values are PARAMETER SYMBOL Output Residual Jitter Output Transition Time Lane-to-Lane Skew Propagation Delay LOS Assert Time LOS De-Assert Time Data-to-Line Silence Response Time Line Silence-to-Data Response Time NOTES: ...
Page 6
Typical Performance Characteristics Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched into the twin-ax cable using an SMA/CX4 adapter card. The chip evaluation board is connected to the output ...
Page 7
FIGURE 4. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx411GRx Operation The QLx411GRx is an advanced quad lane-extender for high-speed interconnects. A functional diagram of one of the four channels in the QLx411GRx is shown in Figure 4. In ...
Page 8
CML Input and Output Buffers The input and output buffers for the high-speed data channels in the QLx411GRx are implemented using CML. Equivalent input and output circuits are shown in Figures 6 and IN[k] P 50Ω 50Ω ...
Page 9
Typical Application Reference Design Figure 8 shows reference design schematics for a QLx411GRx evaluation board with an SMA connector interface. 1.2V Detection threshold reference voltage Loss of signal indicator (Channels 1 and 2) 1.2V Bypass circuit for each V pin: ...
Page 10
... Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...
Page 11
Package Outline Drawing L46.4x7 46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN) Rev 0, 9/09 4.00 6 PIN 1 INDEX AREA (4X) 0.05 TOP VIEW 0.70 ±0.05 SIDE VIEW ( 3. 2.50 5.50 ...