pdi1394p25 NXP Semiconductors, pdi1394p25 Datasheet - Page 34

• Manufacturer Part Number: pdi1394p25
• Description: 1-port 400 Mbps Physical Layer Interface
• Manufacturer: NXP Semiconductors

1. The specified T
2. A pulsed LPS signal must have a duty cycle (ratio of T
3. The maximum value for T
Philips Semiconductors
Table 20. LPS Timing Parameters
NOTES:
The LLC requests that the interface be reset by deasserting the LPS
signal and terminating all bus and request activity. When the PHY
observes that LPS has been deasserted for T
the interface. When the interface is in the reset state, the PHY sets
2001 Sep 06
T
T
T
T
T
T
LPSL
LPSH
LPS_RESET
LPS_DISABLE
RESTORE
CLK_ACTIVATE
1-port 400 Mbps physical layer interface
those specified for the same parameters in the P1394a Supplement (i.e., an implementation of LPS that meets the requirements of P1394a
will operate correctly with the PDI1394P25).
isolation barrier on the LPS signal (e.g., as shown in Figure 8)
before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is
deasserted for less than T
PARAMETER
LPSL
CTL0, CTL1
SYSCLK
D0 – D7
LPS low time (when pulsed) (see Note 1)
LPS high time (when pulsed) (see Note 1)
LPS duty cycle (when pulsed) (see Note 2)
Time for PHY to recognize LPS deasserted and reset the interface
Time for PHY to recognize LPS deasserted and disable the interface
Time to permit optional isolation circuits to restore during an interface reset
Time for SYSCLK to be activated from reassertion of LPS
and T
LREQ
LPS
ISO
RESTORE
LPS_DISABLE
LPSH
(low)
T
LPSL
times are worst–case values appropriate for operation with the PDI1394P25. These values are broader than
does not apply when the PHY–LLC interface is disabled, in which case an indefinite time may elapse
T
.
LPSH
LPS_RESET
(a)
Figure 20. Interface Reset, ISO Low
, it resets
(b)
LPSH
DESCRIPTION
to cycle period) in the specified range to ensure proper operation when using an
T
LPS_RESET
34
the LREQ signal. The timing for interface reset is shown in Figure 20
its CTL and D outputs in the logic 0 state and ignores any activity on
and Figure 21.
(c)
T
RESTORE
0.09
0.021
20
2.60
26.03
15
MIN
—
(d)
PDI1394P25
2.60
2.60
55
2.68
26.11
23
60
MAX
Preliminary data
SV01810
%
nS
UNIT
S
S
S
S
S