saa1575hl NXP Semiconductors, saa1575hl Datasheet - Page 19

• Manufacturer Part Number: saa1575hl
• Description: Global Positioning System Gps Baseband Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.7
The off-chip memories and the on-chip registers are on the
same address and data bus. The routing of the data and
address signals between the on-chip registers and the
off-chip memories is controlled by a block known as the
external bus interface. In addition, certain chip enable
signals are decoded within the block to reduce the amount
of external glue logic required in the complete system.
The address latch, normally required on 80C51 systems,
is implemented within the SAA1575HL. Therefore, no ALE
signal is seen outside the IC and address and data lines
are brought out on separate pins.
1999 Jun 04
handbook, full pagewidth
Global Positioning System (GPS)
baseband processor
The external bus
WRH, WRL, RD
XA
D15 to D0
A4 to A19
A3 to A1
PMCS
Fig.10 SAA1575HL internal address and data routing.
ALE
LE
ADDRESS
LATCH
A1 to A8
19
However, since internally there is still the need to latch the
address from a common address/data bus, signals on the
data bus will be seen to change during the address set-up
cycles.
The lower 3 external address lines are driven directly by
the XA core and are not latched. This allows ‘burst’ code
reads to be performed in which adjacent code locations
are accessed without the need for an address latch cycle.
Signals similar to those used by a standard 80C51 or XA
system are used to control the external bus activity.
D15 to D0
to MMRS
16
DECODER
ADDRESS
ENABLE
MHB469
16
16
3
3
DMCS
A4 to A19
D15 to D0
A3 to A1
WRH, WRL, RD
PMCS
SAA1575HL
Product specification