hcpl-530k-200 Avago Technologies, hcpl-530k-200 Datasheet - Page 7

• Manufacturer Part Number: hcpl-530k-200
• Description: Intelligent Power Module And Gate Drive Interface Hermetically Sealed Optocouplers
• Manufacturer: Avago Technologies

Switching Specifications (R
Over recommended operating conditions: (T
V
*All typical values at 25 C, V
Notes:
10. Common mode transient immunity in a Logic Low level is the maximum tolerable dV
11. Pulse Width Distortion (PWD) is defined as the difference between t
12. Standard parts receive 100% testing at 25 C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25 C, +125 C, and -55 C
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits
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Parameter
Propagation
Delay Time to
Low Output
Level
Propagation
Delay Time to
High Output
Level
Pulse Width
Distortion
Propagation
Delay
Difference
Between Any
Two Parts
Output High
Level Common
Mode Transient
Immunity
Output Low
Level Common
Mode Transient
Immunity
Power Supply
Rejection
1. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (I
2. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together.
3. Pulse: f = 20 kHz, Duty Cycle = 10%
4. The internal 20 k resistor can be used by shorting pins 6 and 7 together.
5. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved
6. The R
7. Use of a 0.1 F bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
8. The difference in t
9. Common mode transient immunity in a Logic High level is the maximum tolerable dV
F(OFF)
by using an external 20 k 1% load resistor. For more information on how propagation delay varies with load resistance, see Figure 8.
section.)
output will remain in a Logic High state (i.e., V
output will remain in a Logic Low state (i.e., V
(Subgroups 1 and 9, 2 and 10, 3 and 11 respectively).
specified for all lots not specifically tested.
= -5 V to 0.8 V) unless otherwise specified.
L
= 20 k , C
L
PLH
= 100 pF represents a typical IPM (Intelligent Power Module) load.
|CM
PSR
Symbol
t
t
PWD
t
t
|CM
PHL
PLH
PLH
PHL
and t
CC
H
-
L
|
|
= 15 V.
PHL
L
between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications
= Internal Pull-up)
Group A
Subgrps.
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
O
O
[12]
< 1.0 V).
> 3.0 V).
Min.
20
220
-225
A
= -55 C to +125 C, V
Typ.*
185
415
150
150
10
10
1.0
PLH
and t
Max.
500
750
600
650
PHL
for any given device.
CC
Units
ns
ns
ns
ns
kV/ s
kV/ s
V
= +4.5 V to 30 V, I
P-P
CM
CM
/dt of the common mode pulse, V
O
/dt of the common mode pulse, V
) to the forward LED input current (I
Test Conditions
I
V
V
C
V
V
I
V
I
V
Square Wave, t
> 5 ns, no bypass
capacitors.
F(on)
F
F
F(off)
CC
O
O
THLH
THHL
L
= 16 mA
= 0 mA,
> 3.0 V
< 1.0 V
= 100 pF,
= 15.0 V,
= 10 mA,
= 0.8 V,
= 2.0 V
= 1.5 V
F(ON)
V
C
V
T
CC
CM
A
L
= 100 pF,
= 25 C
RISE
= 10 mA to 20 mA,
= 15.0 V,
= 1000
, t
FALL
CM
CM
F
, to assure that the
, to assure that the
) times 100.
Fig.
5, 8,
6, 21
Note
3, 4,
5, 6,
7
11
8
9
10
7