w83977tf Winbond Electronics Corp America, w83977tf Datasheet - Page 102

• Manufacturer Part Number: w83977tf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

PM1TMR1
PM1TMR2
PM1TMR3
PM1TMR4
Register
PM1STS1
PM1STS2
PM1CTL1
PM1CTL2
PM1CTL3
PM1CTL4
PM1EN1
PM1EN2
<CR60,61>
<CR60,61>
+1H
<CR60,61>
+2H
<CR60,61>
+3H
<CR60,61>
+4H
<CR60,61>
+5H
<CR60,61>
+6H
<CR60,61>
+7H
<CR60,61>
+8H
<CR60,61>
+9H
<CR60,61>
+AH
<CR60,61>
+BH
9.3.21
Table 9-1:
Address
Bit
2-7
0
1
BIOS_RLS
BM_CNTRL
Reserved
Bit Map Configuration Registers
Bit Map of PM1 Register Block
Name
Power-On
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
7
Reset
Value
6
5
TMR_VAL15
TMR_VAL23
TMR_VAL7
WAK_STS
The BIOS release bit. This bit is used by the BIOS software to raise an event
to the ACPI software. The ACPI software has a corresponding enable and
status bit to control its ability to receive the ACPI event. Setting BIOS_RLS
sets GBL_STS, and it generates an SCI interrupt if GBL_EN is also set.
Writing a 1 to its bit position sets this bit and also sets the BM_STS bit.
Writing a 0 has no effect. This bit is cleared by writing a 1 to the GBL_STS
bit.
This bit is used to set the BM_STS bit and if the BM_RLD bit is also set, then
an SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets
BM_STS.
BM_STS and also clears BM_CNTRL.
Reserved.
D7
0
0
0
0
0
0
0
0
4
3
TMR_VAL14
TMR_VAL22
TMR_VAL6
Writing a 0 has no effect.
D6
0
0
0
0
0
0
0
0
0
2
1
TMR_VAL13
TMR_VAL21
TMR_VAL5
GBL_STS
GBL_EN
D5
-92 -
0
0
0
0
0
0
0
0
BIOS_RLS
BM_CNTRL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TMR_VAL12
TMR_VAL20
TMR_VAL4
Description
BM_STS
D4
0
0
0
0
0
0
0
0
Publication Release Date:March 1998
TMR_VAL11
TMR_VAL19
Wrinting a 1 to BM_STS clears
TMR_VAL3
D3
0
0
0
0
0
0
0
0
0
W83977TF
TMR_VAL10
TMR_VAL18
TMR_VAL2
GBL_RLS
PRELIMINARY
D2
0
0
0
0
0
0
0
TMR_VAL17
Revision 0.62
TMR_VAL1
TMR_VAL9
BM_RLD
D1
0
0
0
0
0
0
0
0
TMR_VAL16
TMR_VAL0
TMR_VAL8
TMR_EN
TMR_STS
SCI_EN
D0
0
0
0
0
0
0